Part Review Datasheet

Thought for 6 mins 37 sec
Thought for 6 sec
Referenced guidance.
Created 4 tasks.
1/4 Inspect current component properties and all 144 symbol pins

Inspect current component properties and all 144 symbol pins

Obtain and interpret the official datasheet pinout

Assign pin orientation, section, and terminal order; remove Pin Group

Verify pin identities and mappings are unchanged and review symbol balance

Thought for 14 sec
Created a thread
Symbol Terminal Audit
Completed
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Thought for 9 sec
Awaiting 1 background task
Received notification from "Symbol Terminal Audit" that it finished — picking the work back up.

flux

The executor has finished. I’m reconciling its report against the requested constraints and independently checking the final terminal metadata before closing.

flux

Reconciled and verified: all 144 pins retain their original identities and footprint mappings. Power is first, Ground last, terminal orders are unique 1–144, Pin Group is cleared, and orientation is balanced 72 left / 72 right.
Datasheet evidence, section counts, and pre-existing mismatches are documented in Symbol Terminal Audit.
Fix pin electrical types
Review footprint geometry
Add datasheet property
Create quality report
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Files

Pins

Symbol

Layout

3D View

REF_CLKOP[1]
Pin Number
A2
REF_CLKON[1]
Pin Number
A1
REF_CLKON[4]
Pin Number
A3
REF_CLKOP[4]
Pin Number
A4
Name
Pin #
Type
Section
Pin Group
Orientation
Order
REF_CLKON[1]
A1
Unspecified
Reference Clock Outputs
Right
53
REF_CLKOP[1]
A2
Unspecified
Reference Clock Outputs
Left
48
REF_CLKON[4]
A3
Unspecified
Reference Clock Outputs
Right
54
REF_CLKOP[4]
A4
Unspecified
Reference Clock Outputs
Left
49
REF_CLKIN[0]
A5
Unspecified
PCIe Reference Clock Inputs & Bias
Left
20
REF_CLKIP[0]
A6
Unspecified
PCIe Reference Clock Inputs & Bias
Left
19
PERN_[1]
A7
Unspecified
PCIe Receive Lanes
Left
27
PERP_[1]
A8
Unspecified
PCIe Receive Lanes
Left
26
PERN_[0]
A9
Unspecified
PCIe Receive Lanes
Left
25
PERP_[0]
A10
Unspecified
PCIe Receive Lanes
Left
24
JTAG__SEL__L
A11
Unspecified
JTAG & Test
Left
111
PERST__L
A12
Unspecified
Configuration & Reset
Left
58
VSS_1
B1
Unspecified
Ground
Left
119
REF_CLKOP[6]
B2
Unspecified
Reference Clock Outputs
Left
51
REF_CLKOP[5]
B3
Unspecified
Reference Clock Outputs
Left
50
VSS_2
B4
Unspecified
Ground
Left
120
GPIO_[15]
B5
Unspecified
GPIO, Port Presence & Status
Left
80
VSS_3
B6
Unspecified
Ground
Left
121
VSS_4
B7
Unspecified
Ground
Left
122
VSS_5
B8
Unspecified
Ground
Left
123
VSS_6
B9
Unspecified
Ground
Left
124
VSS_7
B10
Unspecified
Ground
Left
125
PORT_CFG[0]
B11
Unspecified
Configuration & Reset
Left
61

PI7C9X3G606GPCFCAEX