PD70211ILQ TR Audit

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Completed 6 design checks.
Reading schematic details.
Reading PD70211ILQ TR Audit's report…
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2/3 Verify all terminal numbers, duplicate functions, descriptions, and types

Populate Rev. B Pin Description and Pin Type on all 37 terminals

Verify all terminal numbers, duplicate functions, descriptions, and types

Run component review/ERC checks and summarize results

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Awaiting 1 background task
Received notification from "PD70211 Pin Verification" that it finished — picking the work back up.

flux

The independent pin review has finished. I’m applying its findings to the completion check and will correct any specific discrepancies it identified.

flux

Populated Pin Description and Pin Type for all 37 terminals from Rev. B Table 3-1.
  • Pins 8/9 remain separate, equivalent VPN_IN terminals.
  • Pins 10/11 remain separate, equivalent VPN_OUT terminals.
  • EPAD remains pin 37 and mapped to EP.
  • Independent verification found and corrected one wording discrepancy on pin 2.
  • No component-review or ERC issues were returned.
Fix exposed-pad paste
Add thermal via guidance
Update datasheet revision
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Files

Pins

Symbol

Layout

Preview

WA_EN
Pin Number
33
FB
Pin Number
23
DAO
Pin Number
22
HYST
Pin Number
14
RCLP
Pin Number
18
RREF
Pin Number
4
RCLASS
Pin Number
5
VL
Pin Number
25
CSN
Pin Number
28
VINS
Pin Number
13
SS
Pin Number
17
SUPP_S2
Pin Number
2
RDET
Pin Number
36
VPN_IN_1
Pin Number
8
VSN
Pin Number
19
RFREQ
Pin Number
16
CSP
Pin Number
29
VPN_OUT_2
Pin Number
11
PGND
Pin Number
27
4P_HD_FLAG
Pin Number
34
GND
Pin Number
24
SG
Pin Number
26
EP
Pin Number
37
VPP
Pin Number
35
SYNC
Pin Number
15
SUPP_S1
Pin Number
1
VPN_OUT_1
Pin Number
10
COMP
Pin Number
21
VAUX_VCC
Pin Number
32
4P_AT_FLAG
Pin Number
3
VH
Pin Number
31
VSP
Pin Number
20
HD_FLAG
Pin Number
6
AT_FLAG
Pin Number
7
ENABLE
Pin Number
12
VPN_IN_2
Pin Number
9
PG
Pin Number
30
Name
Pin #
Type
Part Type
Pin Description
Pin Orientation
SUPP_S1
1
Input
Terminal
Data-pair bridge voltage sense input; use 10 kΩ series resistor; referenced to VPN_IN
SUPP_S2
2
Input
Terminal
Diode-bridge voltage sense input connected to the data pairs; use 10 kΩ series resistor; referenced to VPN_IN
4P_AT_FLAG
3
Open Collector
Terminal
Active-low open-drain 4-pair Type-2 classification flag; referenced to VPN_OUT
RREF
4
Programmable
Terminal
Bias-current programming resistor; connect 60.4 kΩ 1% to VPN_IN
RCLASS
5
Programmable
Terminal
PD classification programming resistor input; connect RCLASS to VPN_IN
HD_FLAG
6
Open Collector
Terminal
Active-low open-drain 2-pair HDBaseT classification flag; referenced to VPN_OUT
AT_FLAG
7
Open Collector
Terminal
Active-low open-drain Type-2 classification flag; referenced to VPN_OUT
VPN_IN_1
8
Ground
Terminal
Incoming PoE negative rail and front-end reference ground
VPN_IN_2
9
Ground
Terminal
Incoming PoE negative rail and front-end reference ground
VPN_OUT_1
10
Ground
Terminal
Switched negative rail establishing converter power-ground continuity after PD power-up
VPN_OUT_2
11
Ground
Terminal
Switched negative rail establishing converter power-ground continuity after PD power-up
ENABLE
12
Input
Terminal
Logic enable input for PWM converter; high can force wall-adapter startup
VINS
13
Input
Terminal
Programmable 1.2 V PWM input-UVLO sense input
HYST
14
Output
Terminal
UVLO comparator output; connect hysteresis resistor to VINS
SYNC
15
Input
Terminal
External PWM synchronization clock input; clock is twice desired switching frequency
RFREQ
16
Programmable
Terminal
Switching-frequency programming resistor; connect to GND
SS
17
Programmable
Terminal
Soft-start capacitor node; capacitor to GND also controls fault hiccup timing
RCLP
18
Programmable
Terminal
Light-load pulse-skip threshold programming resistor; ground to disable pulse skipping

PD70211ILQ-TR

PD70211ILQ-TR thumbnail