Part Datasheet Audit

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3/3 Independently verify all 33 descriptions against the datasheet and project

Build complete datasheet-backed descriptions for all 33 terminals

Write Pin Description properties to all terminals

Independently verify all 33 descriptions against the datasheet and project

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Populated and verified datasheet-based Pin Description properties for all 33 terminals. Descriptions include MFP alternate functions, default modes and pulls, interface behavior, supply/decoupling requirements, differential-pair roles, and exposed-pad grounding guidance.
  • Open items: None.
  • Verification: All 33 terminals are present exactly once with non-empty descriptions; no unrelated terminal properties were changed.
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Pins

Symbol

Layout

3D View

GND
Pin Number
33
D2N
Pin Number
26
CKP
Pin Number
27
MFP3
Pin Number
4
D1N
Pin Number
24
MFP8
Pin Number
32
VDD18
Pin Number
11
SION/SIO
Pin Number
12
D0N
Pin Number
22
MFP6
Pin Number
18
XRES
Pin Number
10
D3P
Pin Number
29
SIOP
Pin Number
13
PWDNB
Pin Number
31
CFG1
Pin Number
16
MFP4
Pin Number
6
MFP2
Pin Number
3
MFP1
Pin Number
2
CFG0
Pin Number
5
MFP7
Pin Number
19
D0P
Pin Number
21
VDD
Pin Number
15
CAP_VDD
Pin Number
14
D3N
Pin Number
30
X2
Pin Number
9
D2P
Pin Number
25
MFP0
Pin Number
1
X1/OSC
Pin Number
8
D1P
Pin Number
23
MFP5
Pin Number
7
CKN
Pin Number
28
VTERM
Pin Number
20
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
MFP0
1
Bi-Directional
Multifunction pin: MS UART mode select (1MΩ pull-down; low=Base, high=Bypass), VS or DE/DV video monitor push-pull output, FSYNC push-pull output, or GPIO0. GMSL1 functions also include FSYNC_IN/OUT (frame-sync input with 1MΩ pull-down to ground or frame-sync push-pull output) and CNTL1 push-pull output. MAX96714F power-up default is GPI0 with 1MΩ pull-down. GPIO supports configurable input, push-pull output, or open-drain output and programmable 40kΩ/1MΩ pull-up, pull-down, or no pull.
MFP1
2
Bi-Directional
Multifunction pin: pass-through SDA1/SDA2 I2C data input/open-drain output (40kΩ pull-up to VDDIO), RX1/RX2 UART input (40kΩ pull-up; RX1 default 1Mbps), or GPIO1. GMSL1 functions also include CNTL3 push-pull output and GPI input with 40kΩ pull-down to VDDIO. MAX96714F power-up default is RX1. GPIO is configurable as input or output; GPIO output may be open-drain or push-pull, with programmable internal 40kΩ/1MΩ pull-up, pull-down, or no pull.
MFP2
3
Bi-Directional
Multifunction pin: pass-through SCL1/SCL2 I2C clock input/open-drain output (40kΩ pull-up to VDDIO), TX1/TX2 UART open-drain output (40kΩ pull-up; TX1 default 1Mbps), MS UART mode select (1MΩ pull-down), FSYNC push-pull output, or GPIO2. GMSL1 functions also include FSYNC_IN/OUT (frame-sync input with 1MΩ pull-down to ground or frame-sync push-pull output) and CNTL4 push-pull output. MAX96714F power-up default is TX1. GPIO supports input, push-pull or open-drain output, and programmable 40kΩ/1MΩ pulls.
MFP3
4
Bi-Directional
Primary control-interface multifunction pin: SDA I2C data input/open-drain output with 40kΩ pull-up to VDDIO, or RX UART input with 40kΩ pull-up to VDDIO. MAX96714F power-up function is SDA or RX as selected by CFG0; default control interface is established at power-up.
CFG0
5
Input
Configuration input; voltage is latched at power-up/reset. Resistor-divider level selects the MAX96714F primary control interface (I2C or UART) and initial device address; see CFG0 Input Map (Table 8).
MFP4
6
Bi-Directional
Primary control-interface multifunction pin: SCL I2C clock input/open-drain output with 40kΩ pull-up to VDDIO, or TX UART open-drain output with 40kΩ pull-up to VDDIO. MAX96714F power-up function is SCL or TX as selected by CFG0.
MFP5
7
Bi-Directional
Multifunction pin: LOCK open-drain lock-indication output with 40kΩ pull-up to VDDIO, VS or DE/DV video monitor push-pull output, or GPIO5. MAX96714F power-up default is LOCK. GPIO supports configurable input, push-pull output, or open-drain output and programmable 40kΩ/1MΩ pull-up, pull-down, or no pull.
X1/OSC
8
Input
25MHz crystal/oscillator input. Connect one terminal of a 25MHz crystal here; when using an external oscillator, drive X1/OSC and leave X2 floating.
X2
9
Input
Crystal input. Connect the other terminal of the 25MHz crystal here; leave X2 floating when an external oscillator drives X1/OSC.
XRES
10
Power In
Oscillator bias/reference resistor connection. Connect a 402Ω ±1% resistor from XRES to ground.
VDD18
11
Power In
Top
1.8V analog supply; recommended range 1.7V–1.9V. Place a 10nF decoupling capacitor as close as possible to pin 11 and include at least 10µF bulk decoupling nearby on the PCB.
SION/SIO
12
Bi-Directional
GMSL serial-data input/output: SION is the inverted twisted-pair terminal; SIO is the single-ended coax terminal. CFG1 voltage latched at power-up selects the applicable cable/link configuration.
SIOP
13
Bi-Directional
Noninverted twisted-pair GMSL serial-data input/output. Used for STP operation; CFG1 voltage latched at power-up determines the serial-input/link configuration.
CAP_VDD
14
Power In
External decoupling node for the internal 1.0V core supply. Place a 10nF capacitor from CAP_VDD to PCB ground as close to the pin as possible; provide at least 10µF bulk decoupling nearby.
VDD
15
Power In
Top
Core-supply/LDO input. Apply 0.95V–1.05V to bypass the on-chip LDO, or 1.14V–1.26V to use the internal 1.0V regulator (enable REG_ENABLE then LDO_TEST). Place decoupling to the PCB ground plane as close to the pin as possible.
CFG1
16
Input
Configuration input; voltage is latched at power-up/reset. Resistor-divider level selects MAX96714F coax versus twisted-pair input, GMSL1/GMSL2 startup mode, link/data mode, and related initial serial-link configuration; see CFG1 Input Map (Table 9).
VDDIO
17
Power In
Top
1.8V to 3.3V I/O supply (recommended range 1.7V–3.6V); sets MFP/control-interface logic levels and supplies their internal pull resistors.
MFP6
18
Bi-Directional
Multifunction pin: LMN0 line-fault monitor input or GPIO6; GMSL1 also supports CNTL2 push-pull output. MAX96714F power-up default is GPI6 with 1MΩ pull-down to ground. GPIO supports configurable input, push-pull output, or open-drain output and programmable 40kΩ/1MΩ pull-up, pull-down, or no pull.
MFP7
19
Bi-Directional
Multifunction pin: LMN1 line-fault monitor input or GPIO7; GMSL1 also supports CNTL0 push-pull output. MAX96714F power-up default is GPI7 with 1MΩ pull-down to ground. GPIO supports configurable input, push-pull output, or open-drain output and programmable 40kΩ/1MΩ pull-up, pull-down, or no pull.
VTERM
20
Power In
1.2V MIPI D-PHY termination supply (1.2V ±5%). Decouple to the PCB ground plane close to the pin.
D0P
21
Output
MIPI CSI-2 D-PHY data lane 0 noninverted output; route as the positive member of the D0P/D0N high-speed differential pair.
D0N
22
Output
MIPI CSI-2 D-PHY data lane 0 inverted output; route as the negative member of the D0P/D0N high-speed differential pair.
D1P
23
Output
MIPI CSI-2 D-PHY data lane 1 noninverted output; route as the positive member of the D1P/D1N high-speed differential pair.

MAX96714FGTJ/V+