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I’ll correct the part metadata and pin data first, then rebuild/scale the LGA footprint from the Telit land-pattern evidence and verify sampled pads afterward.
Metadata is updated with corrected supply range, AP variant band notes, and Telit form-factor details. I’m now applying the full pin-table descriptions and type corrections.
The pin table metadata is now updated, including SIMVCC as module-generated outputs, USB_VBUS as a sense input, ground pins as Ground, and reserved pins as no-connect. Next I’m replacing the imported mis-scaled footprint with a 15 x 15 LGA grid using the Telit 1.8 mm pitch / 0.7 mm pad evidence.
Completed the footprint, pin metadata, and description cleanup. I updated the detailed fix log in LE910C1-AP Part Review.
Open items:
  • The detailed Telit hardware guide source is still from mirrored/FCC/Arrow copies; the project uses the official public Telit product brief as the Datasheet URL.
  • If the published library index lags behind project metadata, re-publish/re-index the part.
Suggested next steps:
  1. Re-publish the component so downstream projects pick up the corrected footprint and pin metadata.
  2. Run a visual footprint check against Telit Figure 24 before release.
  3. Add controlled-impedance defaults for RF/USB/SGMII pins if this part will be reused in routed designs.
Review, impedance and export
Check footprint visually
Add impedance defaults
Run full validation
Export validation report

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
GND_A2
A2
Ground
A2. Ground return pad. Connect to solid low-impedance ground plane with stitching per Telit RF/power layout guidance.
SIMVCC1
A3
Power Out
A3. Module-generated SIM 1 supply output, 1.8 V / 2.85 V. Do not drive from an external rail unless Telit documentation explicitly permits it.
~{SIMIN1}
A4
Input
A4. External SIM 1 presence detect input, 1.8 V logic, active low.
SIMIO1
A5
Bi-Directional
A5. External SIM 1 data I/O, 1.8 V / 2.85 V domain, internally pulled up 20 kOhm to SIMVCC1.
SIMCLK1
A6
Output
A6. External SIM 1 clock output, 1.8 V / 2.85 V domain.
SIMRST1
A7
Output
A7. External SIM 1 reset output, 1.8 V / 2.85 V domain.
RESERVED_A8
A8
Not Connected
A8. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
RESERVED_A9
A9
Not Connected
A9. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
RESERVED_A10
A10
Not Connected
A10. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
HSIC_STB
A11
Bi-Directional
A11. HSIC high-speed inter-chip strobe, bidirectional, 1.2 V domain. Route with HSIC_DATA per high-speed guidance.
HSIC_DATA
A12
Bi-Directional
A12. HSIC high-speed inter-chip data, bidirectional, 1.2 V domain. Route with HSIC_STB per high-speed guidance.
USB_VBUS
A13
Input
A13. USB VBUS sense / internal USB transceiver power-detect input; 2.5 V to 5.5 V, max 5 mA per Telit guide. This is not the main module supply.
USB_ID
A14
Input
A14. USB ID analog input. LE910C1-specific pin; follow Telit USB interface guidance and leave/test-point as specified if unused.
ADC_IN1
B1
Input
B1. Analog/digital converter input 1. Keep within Telit-specified analog input range.
RESERVED_B2
B2
Not Connected
B2. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
RESERVED_B3
B3
Not Connected
B3. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
RESERVED_B4
B4
Not Connected
B4. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
RESERVED_B5
B5
Not Connected
B5. Reserved pad. Leave unconnected/floating unless the Telit hardware guide explicitly states otherwise.
DVI_RX
B6
Input
B6. Digital Voice Interface receive input, 1.8 V logic.
DVI_TX
B7
Output
B7. Digital Voice Interface transmit output, 1.8 V logic.
DVI_CLK
B8
Output
B8. Digital Voice Interface clock master output, 1.8 V logic.
DVI_WAO
B9
Output
B9. Digital Voice Interface WAO master output, 1.8 V logic.
I2C_SDA
B10
Bi-Directional
B10. I2C data, bidirectional/open-drain style, 1.8 V logic with internal 2.2 kOhm pull-up to 1.8 V. LE910C1-specific pin.

LE910C1-AP