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DIT4192IPW Datasheet Review

Date: 2026-07-15

Datasheet source

Official Texas Instruments datasheet: https://www.ti.com/lit/ds/symlink/dit4192.pdf

The part metadata was updated so the Datasheet URL points to the official TI DIT4192 PDF.

Part metadata review

Table

Field	Current project value	Datasheet / TI value	Status
Manufacturer	Texas Instruments	Texas Instruments	OK
Manufacturer Part Number	DIT4192_PW_28	DIT4192IPW; tape-and-reel variant DIT4192IPWR	Mismatch / naming issue
Part type	Integrated Circuit	192 kHz digital audio transmitter	OK
Package	PW28 / TSSOP-28 footprint	TSSOP-28, package designator PW	OK
Pin count	28 terminals / 28 footprint pads	28 pins	OK
Description	TI 192 kHz digital audio transmitter with AES-3 / IEC-60958 / EIAJ CP1201 support	Matches datasheet description/features	OK
Datasheet URL	https://www.ti.com/lit/ds/symlink/dit4192.pdf	Official TI datasheet	OK

Key datasheet specs

Function: 192 kHz digital audio transmitter for professional and consumer audio.
Standards: AES-3, IEC-60958, EIAJ CP1201.
Audio formats: I2S, left-justified, right-justified.
Control modes: software serial-control mode and hardware pin-control mode.
Master clock: 128 fS, 256 fS, 384 fS, or 512 fS; maximum MCLK frequency 25 MHz.
Core supply: VDD = 4.5 V to 5.5 V, nominal 5 V.
I/O supply: VIO = 2.7 V to VDD.
Dynamic supply current at 192 kHz: IDD typ 30 mA; IIO typ 1.5 mA at VIO = 3.3 V or 3 mA at VIO = 5 V.
Output driver: on-chip differential line driver on TX+ and TX-.
Operating temperature: -40°C to +85°C.
Package: PW TSSOP-28, JEDEC MO-153 family.

Applied symbol organization assignments

The following properties were assigned directly to the schematic terminals without changing pin numbers, replacing pins, or remapping pins.

Table

Pin	Schematic pin name	Datasheet software-mode name/function	Section	Orientation	Terminal order	Check
1	NC	NC, no connection	NC	Left	19	OK for software mode
2	CDOUT	Control Port Data Output, tri-state	Control	Right	13	OK
3	CCLK	Control Port Data Clock Input	Control	Left	9	OK
4	CDIN	Control Port Serial Data Input	Control	Left	8	OK
5	*CS	CS, active-low Control Port Chip Select Input	Control	Left	10	OK; active-low notation differs only by using `*` prefix
6	MCLK	Master Clock Input	Interface	Left	3	OK
7	VIO	Digital I/O power supply, +2.7 V to VDD	Power	Top	2	OK
8	DGND	Digital Ground	Ground	Bottom	27	OK
9	RXP	AES-3 Encoded Data Input	Interface	Left	7	OK for software mode
10	NC	NC, no connection	NC	Left	20	OK for software mode
11	SCLK	Audio Serial Port Data Clock I/O	Interface	Left	4	OK
12	SYNC	Audio Serial Port Frame SYNC Clock I/O	Interface	Left	5	OK
13	SDATA	Audio Serial Port Data Input	Interface	Left	6	OK
14	NC	NC, no connection	NC	Left	21	OK for software mode
15	*RST	RST, active-low Reset Input	Control	Right	12	OK; active-low notation differs only by using `*` prefix
16	DGND	Digital Ground	Ground	Bottom	28	OK
17	TX-	Transmitter Line Driver Output	Output	Right	17	OK
18	TX+	Transmitter Line Driver Output	Output	Right	18	OK
19	VDD	Digital core power supply, +5 V nominal	Power	Top	1	OK
20	NC	NC, no connection	NC	Right	22	OK for software mode
21	NC	NC, no connection	NC	Right	23	OK for software mode
22	*INT	INT, open-drain active-low interrupt output; requires 10 kΩ pull-up to VIO	Control	Right	14	OK; active-low notation differs only by using `*` prefix
23	NC	NC, no connection	NC	Right	24	OK for software mode
24	NC	NC, no connection	NC	Right	25	OK for software mode
25	BLS	Block Start I/O	Control	Right	15	OK
26	NC	NC, no connection	NC	Right	26	OK for software mode
27	U	User Data Input	Digital	Right	16	OK
28	MODE	Control Mode Input; MODE = 0 for software mode	Control	Right	11	OK

Power pins were ordered first: VDD then VIO. Ground pins were ordered last: DGND pin 8 then DGND pin 16. Other pins were grouped logically between them and distributed left/right to balance the symbol.

Footprint check

The footprint is a 28-pad TSSOP/PW28-style SMD footprint.

Observed footprint characteristics from the embedded KiCad footprint asset:

28 SMD rectangular pads.
Pad pitch: 0.65 mm.
Pad size: 1.6764 mm x 0.3556 mm.
Pad row center spacing: about 5.6388 mm.
Silkscreen/fab value text: PW28.
3D model asset: PW0028A.stp.

Datasheet PW package characteristics:

Package: PW plastic small-outline package, TSSOP-28.
JEDEC family: MO-153.
Body length for 28 pins: 9.60 mm to 9.80 mm.
Body width: 4.30 mm to 4.50 mm.
Overall width: 6.20 mm to 6.60 mm.
Lead pitch: 0.65 mm.
Lead width: 0.19 mm to 0.30 mm.
Package height: 1.20 mm max.

Footprint status: pin count and pitch match the datasheet PW/TSSOP-28 package. The pad size is a PCB land-pattern dimension rather than a package lead dimension, so it is expected to be larger than the lead width. The datasheet package drawing does not provide a full recommended PCB land pattern, so the imported footprint should still be checked against the assembler/fabricator preferred IPC land pattern if this part will be manufactured.

Mismatches and flags

MPN property mismatch: the project property currently says DIT4192_PW_28, while the TI orderable MPN is DIT4192IPW for tube or DIT4192IPWR for tape-and-reel. I did not change this because the latest user instruction only asked to assign orientation/section/order properties.
Symbol represents software mode only: the schematic pin names match the datasheet Software Mode table with MODE = 0. The DIT4192 datasheet also defines a Hardware Mode pin table with alternate functions on several pins. Those hardware-mode aliases are not represented in the current symbol.
Pin electrical type / pin description properties are incomplete: the terminals still show Pin Type: Unspecified, and the detailed pin-description property is not populated. I did not modify these because the requested direct edit scope was orientation, section, and terminal order only.
Footprint land pattern source: the footprint appears dimensionally consistent for PW/TSSOP-28 pitch and pin count, but the TI datasheet provides package dimensions rather than a complete recommended land pattern. Confirm against the intended assembler's land-pattern rules before production.

Datasheet source
Part metadata review
Key datasheet specs
Applied symbol organization assignments
Footprint check
Mismatches and flags

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