Compact PCB Design for WINO

Applied changes.

0:08

nets {

net VBAT = U2:VCC, J4:P1, U5:VBAT, C13:P1, C10:P1, J3:VCC, U6:EN, U6:IN;

net 3V3 = U1:IO0, U6:OUT, C7:P1, R3:P1, C2:P1, C8:P1, C6:P1, U4:10, U4:9, U4:VDD, U3:V_BCKP, U3:VCC, U1:3V3, M1:3.3V, R4:P1, C12:P1, C5:P1, C4:P1, C3:P1, C1:P1, R6:P1, U1:EN, C11:P1;

net GND = GND:GND, J3 GND - J4 P2:GND, C4:P2, C3:P2, J3 GND - J3 GND:GND, J3:G6, J3:G2, J3:C5, J3:G4, J3:G1, U3 GND_2 - U3 GND_3:GND, M1:GND, R1 P2 - R2 P2:GND, R1:P2, C9:P2, R2:P2, U6:GND, U3:GND_2, U3:GND_1, C1:P2, J1 SHELL_GND__3 - U1 GND:GND, U1:1, M1:AD0, U4 PGND - U5 VSS:GND, J2:GND_3, C6:P2, C10:P2, J3:G3, U2:GND, C13:P2, J2:GND_1, U1:2, C7:P2, J4:P2, U4:GND, U4:PGND, U5:VSS, U3:GND_3, C2:P2, J1:SHELL_GND__3, J1:SHELL_GND__2, J1:SHELL_GND__1, J1:SHELL_GND, J1:GND__1, C5:P2, U3:GND_4, C11:P2, Q1:E, C8:P2, C12:P2, J2:GND_2, J3:G5, J1:GND;

net SIM_RX = J3:I/O, U1:IO18, U2:RXD;

net USB_CC1 = R1:P1, J1:CC1;

net I2C_SCL = U1:IO9, R4:P2, M1:SCL, U4:SCL;

net USB_CC2 = J1:CC2, R2:P1;

net VBUS_5V = U5:VIN, C9:P1, J1:VBUS__1, J1:VBUS;

net SIM_RST = Q1:C, J3:CLK, U2:RST, R6:P2, J3:RST;

net I2C_SDA = M1:SDA, U1:IO8, U4:SDA, R3:P2;

net GPS_RF = J2:SIGNAL, U3:RF_IN;

net MAX_INT = U4:~INT, U1:IO10;

net USB_D+ = J1:DP1, U1:IO20, J1:DP2;

net SIM_TX = U1:IO17, U2:TXD;

net SIM_PWRKEY_CTRL = R5:P2, U1:IO12;

net USB_D- = U1:IO19, J1:DN1, J1:DN2;

net GPS_RX = U1:IO16, U3:TXD1;

net GPS_TX = U1:IO15, U3:RXD1;

net SIM_PWRKEY_BASE = R5:P1, Q1:B;

}

6 days

replacing SIM800L and adding termination parts...

4:24

Running design review.

Analyzing the schematic.

6 days

Added 5 components and Removed 1 component

0:09

Added 1x SIM800L as U2 (Pins: ISINK0, UART_DTR, GND::38, ROW4, VRTC, FM_ANT_N, PCMIN, BPI_BUS1, SIM_CLK, GND::8, GND::58, GND::85, GND::87, ISINK1, GND::6 ... and 73 more)

Added 3x Generic Resistor as R7, R8, R9 (Pins: P2, P1)

Added 1x Generic Capacitor as C14 (Pins: P1, P2)

Removed U2

⚠️ Removed components had their net connections destroyed. Use the connections tool with a `view` action to verify connectivity and re-wire any lost connections.

6 days

Set Resistance to "10kΩ" on R6, Set Role to "Pull-Up" on R6, and 4 more changes

0:04

Set R6's Resistance to "10kΩ"

Set R6's Role to "Pull-Up"

Set R6's Role Details to "SIM800L SIM_RST pull-up to 3V3"

Set C10's Capacitance to "100nF"

Set C10's Role to "Decoupling"

Set C10's Role Details to "High-frequency bypass on VBAT rail near SIM800L and power entry"

6 days

flux

0:11

I replaced the placeholder modem with a full-pin SIM800L and I am now doing the cascading rewire by pin function rather than pin number. I am also enforcing the requested physical constraints next so the modem antenna area and top-side placement are explicit before final validation.

6 days

rewired modem core nets and hit layout rule errors

5:21

Started: rewiring full-pin modem and applying layout constraints

Working.

6 days

Updated 12 connections

0:59

Connected U2:VBAT, U2:VBAT, C13:P1, C10:P1, C14:P1, J4:P1, U5:VBAT, U6:IN, U6:EN to ^VBAT

Connected U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, C14:P2 to ^GND

Connected U2:UART_TXD, U1:IO17 to ^SIM_TX

Connected U2:UART_RXD, U1:IO18 to ^SIM_RX

Connected U2:SIM_DATA, J3:I/O to ^SIM_DATA

Connected U2:SIM_CLK, J3:CLK to ^SIM_CLK

Connected U2:SIM_RST, J3:RST, R6:P2 to ^SIM_RST

Connected R6:P1 to ^3V3

Connected U2:VSIM, J3:VCC to ^VSIM

Connected U2:SIMPRE to ^SIM_DET

Connected Q1:C, U2:PWRKEY to ^SIM_PWRKEY

Disconnected J3:I/O, J3:CLK, J3:RST, J3:VCC, Q1:C, R6:P2

nets {

net 3V3 = R6:P1, U1:IO0, U6:OUT, C7:P1, R3:P1, C2:P1, C8:P1, C6:P1, U4:10, U4:9, U4:VDD, U3:V_BCKP, U3:VCC, U1:3V3, M1:3.3V, R4:P1, C12:P1, C5:P1, C4:P1, C3:P1, C1:P1, U1:EN, C11:P1;

net GND = GND:GND, U2 GND - C14 P2:GND, C14:P2, U2:88, U2:87, U2:86, U2:85, U2:84, U2:83, U2:82, U2:81, U2:80, U2:79, U2:78, U2:77, U2:76, U2:73, U2:72, U2:71, U2:67, U2 GND - U2 GND:GND, U2:58, U2:45, U2:44, U2:43, U2:41, U2:39, U2:38, U2:37, U2:35, U2:8, U2:6, U2:2, J3 GND - J4 P2:GND, C4:P2, C3:P2, J3 GND - J3 GND:GND, J3:G6, J3:G2, J3:C5, J3:G4, J3:G1, U3 GND_2 - U3 GND_3:GND, M1:GND, R1 P2 - R2 P2:GND, R1:P2, C9:P2, R2:P2, U6:GND, U3:GND_2, U3:GND_1, C1:P2, J1 SHELL_GND__3 - U1 GND:GND, U1:1, M1:AD0, U4 PGND - U5 VSS:GND, J2:GND_3, C6:P2, C10:P2, J3:G3, C13:P2, J2:GND_1, U1:2, C7:P2, J4:P2, U4:GND, U4:PGND, U5:VSS, U3:GND_3, C2:P2, J1:SHELL_GND__3, J1:SHELL_GND__2, J1:SHELL_GND__1, J1:SHELL_GND, J1:GND__1, C5:P2, U3:GND_4, C11:P2, Q1:E, C8:P2, C12:P2, J2:GND_2, J3:G5, J1:GND;

net I2C_SCL = U1:IO9, R4:P2, M1:SCL, U4:SCL;

net CHG_STAT = U5:STAT;

net VBUS_5V = U5:VIN, C9:P1, J1:VBUS__1, J1:VBUS;

net I2C_SDA = M1:SDA, U1:IO8, U4:SDA, R3:P2;

net MAX_INT = U4:~INT, U1:IO10;

net USB_D+ = J1:DP1, U1:IO20, J1:DP2;

net SIM_TX = U1:IO17, U2:UART_TXD;

net SIM_PWRKEY_CTRL = R5:P2, U1:IO12;

net USB_D- = U1:IO19, J1:DN1, J1:DN2;

net GPS_RX = U1:IO16, U3:TXD1;

net VBAT = U6:EN, U6:IN, U5:VBAT, J4:P1, C14:P1, C10:P1, C13:P1, U2:42, U2:1;

net CHG_PROG = U5:PROG;

net GPS_TX = U1:IO15, U3:RXD1;

net SIM_PWRKEY_BASE = R5:P1, Q1:B;

net SIM_RX = U2:UART_RXD, U1:IO18;

net SIM_DATA = U2:SIM_DATA, J3:I/O;

net SIM_CLK = U2:SIM_CLK, J3:CLK;

net SIM_RST = U2:SIM_RST, R6:P2, J3:RST;

net VSIM = U2:VSIM, J3:VCC;

net SIM_DET = U2:SIMPRE;

net SIM_PWRKEY = Q1:C, U2:PWRKEY;

}

6 days

recovering layout selectors and validating remaining blockers...

0:24

Running design review.

Analyzing the PCB layout.

Started: recovering layout selectors and validating remaining blockers

6 days

Stopped due to a problem. Please try again.

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Design Notes

WINO architecture decisions

Board size target: 60 mm x 40 mm.
Stackup target: 2-layer PCB with all components on top and solid bottom ground plane.
Main MCU: ESP32-S3 with native USB used for programming over USB-C.
Cellular modem: SIM800L powered directly from LiPo battery rail.
GPS: NEO-6M module with external antenna connector.
Sensors: MPU-6050 and MAX30102 on shared 3.3 V I2C bus.
I2C pull-ups: 4.7 kOhm to 3.3 V on SDA and SCL.
Logic rail: AP2112K-3.3.
Battery charging: single-cell LiPo charger from USB-C 5 V input.
USB-C sink configuration: CC1 and CC2 each use 5.1 kOhm pulldown resistors to GND.
SIM800L control: GPIO-driven PWRKEY and reset wiring, UART link to ESP32-S3.
Placement constraint: keep SIM800L physically isolated from GPS and I2C sensors.
Routing constraint: keep I2C and UART traces short and direct.

WINO architecture decisions

Reviews

Documents

design-notes

Project Specification

Assets

Assets are files uploaded to this project which can be used in various ways.

Project Name

Description

Compact 60 mm x 40 mm child safety wearable PCB with ESP32-S3, SIM800L GSM, NEO-6M GPS, MPU-6050, MAX30102, USB-C charging/programming, LiPo battery input, and test-pointed I2C/UART power rails. Target layout is 2-layer with all components on top, bottom ground plane, short direct I2C/UART routing, and GSM placement isolated from GPS and sensor sections.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor	Qty 1
Arrow	$0.61–$0.66
Digi-Key	$1.04–$1.57
LCSC	$1.94
Mouser	$1.70
TME	$0.90
Verical	$1.23–$1.98

Controls

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