The last confirmed routing result had 9 airwires, mainly around the USB-C differential escape. A final USB-C breakout recovery pass was started, but I could not retrieve its completed report.
Gerbers and pick-and-place files remain withheld until a live check confirms zero airwires and no blocking DRC faults.
Exact Sanwa JLF/JLX and Seimitsu cross-compatibility remains provisional because complete manufacturer mounting drawings were unavailable.
Button-nut clearance, deck motion, structural strength, cable pull resistance, and swap time require a physical prototype.
PC and supported Switch-class operation targets GP2040-CE. Native PS5 and Xbox One authentication still requires licensed hardware or an external compatible adapter.
Electronics schematic and PCB are implemented, but this revision is not a fabrication release. The schematic is complete enough for design review; the PCB is 120 × 55 mm and substantially routed. Final verification reports 9 airwires and 7 redundant-copper groups after the mandated two additional routing iterations. Known cross-net overlapping-copper errors were removed. Gerber/drill and pick-and-place export are blocked until routing is completed and DRC is clean.
Product
Large serviceable USB arcade stick with one digital joystick, eight gameplay buttons, and Start, Select/Back, Home/Guide, and Mode. Controls connect through replaceable harnesses with 2.8 mm quick-disconnects at switches and locking JST XH board headers.
Electrical Architecture
USB bus powered, USB-C USB 2.0 device.
RP2040 MCU with W25Q16 QSPI flash, 12 MHz crystal, AP2112K-3.3 LDO, USB ESD protection, VBUS TVS and resettable fuse.
Two 5.1 kΩ USB-C CC pull-downs.
Active-low switch inputs sharing harness ground.
BOOTSEL and RUN/RESET service buttons.
SWD and labeled test access for VBUS, 3V3, GND, D+/D−, RUN, SWDIO and SWCLK.
Input and GPIO Map
Table
Function
RP2040 GPIO
Harness
UP
0
J2 pin 2
DOWN
1
J2 pin 3
LEFT
2
J2 pin 4
RIGHT
3
J2 pin 5
B1–B4
4–7
J3 pins 2–5
B5–B8
8–11
J4 pins 2–5
START
12
J5 pin 2
SELECT/BACK
13
J5 pin 3
HOME/GUIDE
14
J5 pin 4
MODE
15
J5 pin 5
J2/J3/J4/J5 pin 1 is GND. Inputs use firmware pull-ups and close to GND.
Mechanical Interface
PCB outline: 120 × 55 mm maximum and implemented at 120 × 55 mm.
Tray: 130 × 60 × 3 mm, centered at enclosure coordinates (−80, −85) mm.
Mount centers in enclosure coordinates: (−130,−105), (−130,−65), (−30,−105), (−30,−65) mm.
Equivalent PCB-local pattern about board center: (±50, ±20) mm.
Tray slots are 8 × 3.4 mm, Y-oriented, for M3 hardware.
PCB underside target Z27 on 8 mm insulating standoffs; reserved envelope through Z52.
USB-C J1 is placed at the board edge. Mechanical rear opening remains provisional; use a short internal panel-mount USB-C extension if direct mating cannot be qualified with the actual enclosure cable/plate.
PCB Construction
Current layout uses a 1.30 mm four-layer stackup: top signal, internal ground, internal power, bottom signal; standard 0.6/0.3 mm through vias. This exceeds the minimum two-layer-via allowance and supports USB return-path continuity. Board fill ratio is approximately 21.7%.
Firmware and Compatibility
Target firmware is GP2040-CE using a custom RP2040 board definition matching the GPIO table. PC USB and open-firmware-supported Nintendo Switch-class operation are in scope. Native PS5 and Xbox One authentication are out of scope; use a supported external adapter/authentication device where required.
Verification and Release Gates
Schematic connectivity exists for the RP2040, flash, crystal, power, USB, harnesses, recovery buttons and debug access.
Final DRC: 9 airwires; 7 redundant-copper groups; no reported overlapping-copper errors in the final focused check.
USB-C breakout remains blocked by connector-pin keepout/escape geometry, with USB_DM_CONN and USB_DP_CONN marked unrouteable by the autorouter.
Other exact airwires: B1, LEFT, SWDIO, VBUS_RAW, two GND connections, USB ESD-to-breakout D−, USB ESD-to-breakout D+, and J1 DP1-to-DP2.
29 generic passives lack explicit manufacturer part numbers; acceptable for prototype sourcing only, not turnkey assembly release.
Gerber/drill and pick-and-place export are blocked by airwires. BOM and board STPZ were exported safely.
Manufacturing Expectations
0603 generic passives, robust through-hole JST XH harness headers, and hand-assembly-friendly service buttons are preferred. Verify USB-C connector soldering, QFN exposed pad, crystal placement, and connector pin-1 labels before assembly. Do not order PCB fabrication from this revision until the routing blockers above are resolved and DRC rerun.
Related Files
See Power Budget, Firmware Starter, Board Bring-Up Plan, Electronics Design Report, and Mechanical Design Report.