Vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Definición de la entidad
entity TwoBitAdder is
  port (
    a, b : in STD_LOGIC_VECTOR(1 downto 0);
    sum : out STD_LOGIC_VECTOR(1 downto 0);
    carry_out : out STD_LOGIC
  );
end entity TwoBitAdder;

-- Implementación de la entidad
architecture behavioral of TwoBitAdder is
  signal carry : STD_LOGIC_VECTOR(1 downto 0);
begin
  -- Suma de los bits sin tener en cuenta el posible acarreo
  sum(0) <= a(0) xor b(0);
  sum(1) <= a(1) xor b(1);

  -- Cálculo del acarreo
  carry(0) <= a(0) and b(0);
  carry(1) <= (a(1) and b(1)) or (sum(0) and (a(1) xor b(1)));

  -- Conexión del acarreo a su respectiva salida
  carry_out <= carry(1);
end architecture behavioral;