I started two separate projects and recorded the original unequal-size requirements.
FC project: latest saved state has 36 components and 27 nets, including STM32F405, ICM-42688-P gyro, 16MB flash, USB-C, USB protection, clock oscillator and 3.3V regulator parts. Electrical capture progressed, but I haven’t completed the final connectivity, power and firmware-compatibility review. The 39 × 39mm size is recorded—not yet implemented as a finished PCB layout.
ESC project:4 components and 3 nets form a provisional battery-voltage divider/filter and TVS branch. The unloaded divider was simulated; inspection found 0 ERC errors and 1 warning. This is not yet a working motor ESC.
Still unresolved: actual ESC bare-board geometry within the published 40.9 × 44.9mm heatsink-inclusive envelope, exact ten-pin cable mapping, and verified OX32 controller/firmware access. Motor power stages, matching pad positions/silkscreen, PCB routing and 55A load/thermal validation remain unfinished; neither board is manufacturing-ready or an exact verified copy.
Bench development and eventual multirotor integration after electrical, firmware and assembled-board tests. No flight or production readiness claim. Remove propellers for every bring-up test.
What the Device Should Do
Read inertial and pressure sensors, run flight-control firmware, log blackbox data, exchange receiver/GPS/VTX/telemetry data, and provide four motor and two servo signals. Supply external accessories from battery and allow receiver/GPS operation from USB without backfeeding either source.
Main Features
Reference targets: STM32F405, ICM42688P, SPA06-003, AT7456E, 16MB blackbox, USB-C, six UART roles, SWD/reset/boot, camera/video, buzzer, LEDs, receiver, GPS/compass and HD VTX. Proprietary Bluetooth/app activation and wireless flashing are not established and are deferred, not emulated.
Mechanical System Architecture
Text
39x39mm FC -- stack spacers / signal harness -- separate ESC
heatsink + motors
Original unequal dimensions explicitly approved. FC reference height4.9mm; mounting spacing30.5x30.5mm, diameter4mm side-open holes. ESC envelope40.9x44.9x8mm includes heatsink, not verified bare PCB. No enclosure is in scope. Notch geometry, exact pad coordinates and mating connector numbering are unresolved; no board outline or holes authored.
Power tree is proposed, not wired. Never tie USB VBUS directly to battery-derived5V.
Hardware Subsystems
Compute: sourced U1 STM32F405RGT6; supply, VCAP, reset, boot, clock and debug support still unconnected. Library search metadata says32-LQFP despite64 terminals and description64-LQFP: footprint must be checked before acceptance for manufacture.
IMU: sourced U2 ICM-42688-P. Reserved pin7 must go toGND;2,3,10,11 may be NC orGND. VDD bypass100nF and2.2uF, VDDIO10nF X7R per extracted application data. Quiet rail not designed yet.
Storage: U3 W25Q128JVSIM TR 128Mbit (=16MB), candidate single-SPI blackbox. Supply3.0–3.6V supports133MHz condition. WP and HOLD must be kept inactive for single-SPI use; JEDEC/driver compatibility pending.
MCU decoupling:100nF per VDD pair plus4.7uF bulk, VDDA100nF+1uF. Each VCAP requires2.2uF, ESR<2ohm; never attach VCAP to3V3. NRST recommended100nF to ground; internal pull-up exists.
Pressure: SPA06-003 exact library query returned no match; unavailable named part is not silently substituted. Public manual also mentionsSPA06-001: suffix discrepancy remains open.
OSD: AT7456E library candidate found, not added; pin/supply/3V3-control and video application evidence still needed.
Power and protection: all regulators, source selection and sensing deferred pending complete per-load budget and datasheets.
Interfaces and Connections
External roles intended: UART1 Bluetooth (deferred);UART2 receiver;UART3 HD VTX;UART4 GPS;UART5 RX ESC telemetry;UART6 alternate receiver. CompassI2C; camera/video; buzzer;LED;RSSI;servoS5/S6. Exact connector pin order is not established.
Public Betaflight Support Explorer https://support.betaflight.com/targets/SPEEDYBEEF405V5 provided reference mappings: motorsPB1/PB0/PB10/PB11;UART1PA9/PA10;UART2PA2/PA3;UART3PC10/PC11;UART4PA0/PA1;UART5RX PD2;UART6PC6/PC7. GyroSPI1 PA5SCK/PA6MISO/PA7MOSI,PA4CS,PC4EXTI,PB15CLKIN. FlashSPI3 PB3SCK/PB4MISO/PB5MOSI,PC12CS. SYSTEM_HSE_MHZ8. These are SOURCE REQUIREMENTS, not actual wired pins at this checkpoint. Exact MCU alternate functions/control levels and gyroCLKIN implementation must be checked before wiring. Raw GitHub URL returned404; pin map must be archived to a stable revision before compatibility release.
Manual identifies eight solder functions M4/M3/M2/M1/TLM/current/GND/VBAT but NOT a verified ten-contact map. No guessed ten-pin connector added. Independent named solder interfaces may proceed after electrical verification.
Power and Runtime Expectations
3–6S input,25.2V fully charged6S. Depleted-input planning assumption9V (3V/cell), subject to battery cutoff requirement. No charging on FC. No runtime target given. Input transients from ESC must be characterized;25.2V-only ratings are insufficient.
Power Tree and Power Budget
Manufacturer target is2.5A TOTAL5V and2.5A9V, not per pad. Distinct4.5V receiver/GPS rail target behavior includes USB power. External actual loads remain unspecified.
Table
Rail
Planned consumers
Budget status
5V
camera,buzzer,LED strips,servo supply and internal logic conversion
12.5W total reference envelope; allocation/servo stall peaks unresolved
9V
HD/analog VTX
22.5W total reference envelope; VTX burst/startup unresolved
3V3
MCU,flash,IMU,barometer,pullups
Typical and peak currents not yet extracted; no regulator selected
4.5V
receiver,GPS
USB enumeration/current limits and exact load peaks unresolved; not equivalent to5V
Full two-BEC envelope35W; at assumed85% efficiency and9V minimum battery, reflected input35/(9*0.85)=4.58A before any loads not included in the5V envelope. At25.2V this is1.63A. These are planning calculations, NOT verified consumption or regulator capability. Do not double-count internal logic if included within2.5A5V total; if user needs2.5A external5V PLUS logic, increase budget. Complete per-consumer idle/typical/peak table before selecting every power-path part. USB-only mode must disable9V/5V high-power accessories and budget enumeration/startup receiver/GPS loads. Transient amplitude/duration, fuse derating, protection clamp and capacitor DC-bias/ripple/thermal calculations remain open.
Manufacturing and Assembly Expectations
Compact SMD prototype; layer count and fab not selected. No silent named-silicon substitutions. MCU package/footprint quality must be verified. No manufacturing exports; no layout placement/routing in this pass.
Firmware-Relevant Hardware Requirements
Advertised reference targetSPEEDYBEEF405V5 is not yet proven reusable. Until all mappings,8MHz clock,IMU clock/alignment, flash and barometer drivers, power controls, sense calibration and defaults match, a NEW prototype target is required. Never reuse current-meter scale36 for a new sensor without measured transfer calibration. Boot/DFU andSWD are intended but not wired. Firmware Getting Started and Board Bring-Up files are deferred until actual wired circuits exist; no misleading init examples for unconnected pins.
Physical Design Expectations
FC39x39mm approved; reference4.9mm assembly height is not a guaranteed prototype component-height limit. Preserve mounting spacing only once authoritative side-opening geometry is available. Original pad coordinates/silk cannot be recovered precisely from image-only manual. Mechanical work held for later phase.
Important Design Decisions
Separate unequal-size projects; new compatible prototype, not verified clone. Primary ICs added early from library; no guessed ten-pin harness. Proprietary radio/app excluded pending evidence. No regulator selection before full budget.
Assumptions
9V low battery and85% conversion efficiency are conservative planning assumptions, not datasheet claims. No backup battery planned. Reference page specs are commercial targets, not demonstrated board performance.
Change Notes
2026-10-07: resolved equal-size conflict, renamedFC, updated description/link; added3 primaryICs. Source-backed support facts and public pin map collected. Schematic positioning tool mutate_schematic_arrangement is not exposed in available namespaces despite skill requiring arrange-before-wire: this specifically blocks drafting and subsequent wiring under current procedure. NoPCB mutations made.
Checkpoint and Blockers
Completed: identity, approved size resolution, separate-project link, specification, reference review update, primary sourcing/addition and initial datasheet extraction. Read-only schematic inspection confirms3 components and0 nets. ERC reports95 ERRORS:86 floating pins and9 missing-power findings; these are genuine incomplete-circuit errors, not accepted false positives. No coherent block is electrically completed. Analog simulation not run.
Failed/blocked: coherent wired MCU/clock/reset/boot/SWD/USB,IMU and flash blocks — required schematic arrangement tool unavailable. Power — full per-load peak facts/source path not finished; no regulator chosen. Barometer — named part missing. OSD and remaining interfaces — unattempted beyond candidate/source research. Connector — authoritative ten-pin numbering absent. Analog/power simulation — unattempted, no analog circuit built. No production/flight readiness.