自动布线问题解决
Thought for 36 sec
我查到的常见嘉立创免费/优惠门槛里，核心尺寸条件基本都是：
- 1–4 层板
- 长宽在 10cm × 10cm 以内
- 常见活动里会写成 5 pcs / 单片
- 一般还会附带“常规工艺”限制，比如标准板厚、常规表面工艺、标准铜厚等
- 很多活动/免费券还会带上 新用户、指定下单渠道、月度次数限制 之类条件
你的板子是：
- 100mm × 70mm
- 4 层板
从外形尺寸看，它是落在“10cm × 10cm 以内”这个常见门槛里的。
也就是说：
也就是说：
- 尺寸本身：符合常见免费/优惠尺寸区间
- 层数本身：也符合常见 1–4 层活动范围
能不能“免费出样”，不只看尺寸和层数，还取决于这几个条件是否同时满足：
- 你账号当前有没有对应免费券 / 新人活动资格
- 是否要求常规工艺
- 是否限制板厚、表面处理、颜色、拼板方式
- 是否要求 5片内、单片、不拼特殊工艺
- 活动是否还在有效期内
- 如果按常规 4 层板工艺下单，这块 100×70mm 在“常见活动尺寸”里是有机会命中免费/优惠的
- 但我不能仅凭尺寸断言一定免费
- 最可能的情况是：
- 尺寸/层数 满足活动外框
- 最终能否免费，要看你账号和工艺选项
- 尺寸：符合常见免费打样尺寸门槛
- 4层：也在常见活动支持范围内
- 是否一定免费：不一定，要看账号资格 + 工艺是否标准
如果你愿意，我下一步可以继续帮你做两件事之一：
- 按嘉立创常规免费/低价工艺约束，反推你这块板哪些参数别乱改
- 直接整理一版“下单前检查清单”，让你下单时更容易命中优惠。
列出工艺约束
下单检查清单
检查当前设置
评估缩小尺寸
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PCB Layout Rule Audit - E-Ink Word Learner
Date: 2026-05-22
Scope
Audit of the current PCB placement against the strict 4-layer placement and routing constraints supplied by the user.
Current Board State
- Board: 100 mm x 70 mm, rectangle, 3 mm corner radius.
- Stackup: 4 copper layers.
- L1 Top Copper: Signal.
- L2 Mid-Layer 1: Ground Plane.
- L3 Mid-Layer 2: Power Plane.
- L4 Bottom Copper: Signal.
- Current placement uses both Top and Bottom layers.
- Existing routing/airwires are not clean after recent placement changes; routing must be regenerated under the new rules.
Summary Verdict
Current placement is only partially compliant. The stackup matches the requested 4-layer intent, but multiple placement rules are violated, especially same-layer decoupling, TVS/ESD proximity to the USB connector, low-speed pull resistor layer assignment, and board-edge/antenna/keepout validation. The layout should be corrected before any routing attempt.
Pass / Fail Matrix
Table
| Rule Area | Status | Findings | Required Fix |
|---|---|---|---|
| 4-layer stackup | PASS | L1 signal, L2 ground plane, L3 power plane, L4 signal are present. | Keep current stackup. Verify L2 remains continuous GND and L3 split islands do not create high-speed reference gaps. |
| ESP32 antenna placement | PARTIAL | U1 is at the top edge with antenna overhang. This is directionally correct. However aggregate component bounds extend beyond board top, so the overhang must be confirmed as antenna-only, not full module body/copper. | Add/verify explicit antenna keepout. No copper, traces, vias, or components in antenna region on all layers. |
| Decoupling same-layer rule | FAIL | U4 is on Top, but C10 and C11 are on Bottom. J2 is Top, but C12 and C13 are Bottom. J6 is Top, but C14, C15, C20, C21, C22, C23, C24, C25 are Bottom. ESP32 C2/C3 are Top but appear too far from U1 power pin area. | Move decoupling/bulk caps to same layer as their target IC/connector and close to target power pins. For U4 move C10/C11 to Top near VDD pins. For J2 move C12/C13 to Top near VDD/VSS. For J6 move panel rail caps to Top adjacent to FPC pins. Re-place U1 C2/C3 tighter to U1 3V3/GND return path. |
| Power path decoupling | PARTIAL | U2 and C4/C5/C6/C7/L3 are all Top and clustered, generally compliant. U3 and C8/C9 are Top and nearby. | Keep power regulator/charger caps Top. Tighten loop area during routing with short via-to-plane return and wide power pours. |
| ESD/TVS placement | FAIL | D1 USBLC6 is about 19 mm from J1. User rule requires TVS immediately adjacent to external connector and signals must pass through TVS pad before any via/internal routing. | Move D1 directly beside J1 D+/D- pins, between J1 and U1. USB_DP/USB_DM must flow J1 -> D1 pads -> U1, no via before D1. |
| USB differential pair placement | FAIL until reroute | J1, D1, U1 are not in an optimal short straight chain. D1 is too far from J1. Existing route/airwire state is invalid after placement. | Move D1 adjacent to J1. Route USB_DP/USB_DM as coupled pair on Top referenced to L2 GND, constant spacing, mirrored corners/vias if vias are unavoidable, length match within 5 mil. Prefer no vias. |
| Pull-up / pull-down resistor layer rule | FAIL | R1, R2, R3, R6, R7 are Top despite being static/low-speed pull resistors. R8 is Bottom and compliant. R10 is a strap/config resistor on Bottom and acceptable. | Move R1, R2, R3, R6, R7 to Bottom unless they must be on Top for connector flow or manufacturing constraints. For USB-C CC pull-downs, Bottom is acceptable only if vias do not compromise connector simplicity; otherwise note exception. |
| Series impedance resistors | N/A / Not present | No explicit USB/SPI/I2S series damping resistors are present in the inspected design. | If added later, place same layer as source and close to driving pin. |
| Crystal oscillator rules | N/A | ESP32-S3-WROOM module includes its crystal internally; no external crystal footprint is present. | No external crystal action required. Maintain antenna keepout. |
| Top/Bottom routing orthogonality | PENDING | Existing routing is not final/clean after placement. | During routing, enforce Top as primarily horizontal and Bottom as primarily vertical. |
| 90-degree / acute angle rule | PENDING | Existing routing is not final and still has many airwire errors. | When rerouting, use 135-degree/arc corners only. |
| 3W spacing | PENDING | Requires post-routing check. | Apply at routing stage: minimum edge-to-edge spacing = 2x trace width for parallel signals. |
| Plane integrity / no cross-gap | PENDING | L2 is GND plane and L3 is power plane. Actual power split geometry must be reviewed after fills/routing. | Keep L2 continuous under USB/SPI/I2S/clock-like signals. Do not route high-speed or medium-speed nets over gaps. |
| GND stitching at high-speed vias | PENDING | Requires routing review. | If USB or other high-speed nets transition layers, add adjacent GND stitching vias next to each signal via. |
| 20H power plane pullback | PENDING | Stackup dielectric distance between L2 GND and L3 power is approximately 0.711 mm core between planes in current stackup. 20H pullback target is about 14.22 mm if applied strictly to the L3 power plane edge relative to GND. | Implement/verify L3 power copper pullback from board edge. This may be large for a 100 x 70 mm board; confirm if strict 20H is required or if fab/EMI constraints allow practical relaxation. |
| Power routing star topology | PENDING | Placement puts battery/charger left-lower and regulator lower-middle, which is reasonable, but routing is not yet validated. | Use wide VBAT/VBUS/3V3 pours or traces. Avoid daisy chaining; route 3V3 from U2 output to load branches in star/fanout style. |
Critical Placement Violations To Fix Before Routing
- Move USB TVS D1 immediately adjacent to J1.
- Move U4 decoupling C10/C11 from Bottom to Top, close to U4 VDD pins.
- Move J2 supply caps C12/C13 from Bottom to Top, close to J2 VDD/VSS.
- Move J6 panel rail caps C14/C15/C20/C21/C22/C23/C24/C25 from Bottom to Top adjacent to J6 pins, unless mechanical constraints require documented exceptions.
- Move static pull resistors R1/R2/R3/R6/R7 to Bottom where practical.
- Tighten U1 3V3 decoupling C2/C3 near U1 power/GND return path.
- Confirm ESP32 antenna keepout on every copper layer and prevent bottom-layer copper/routing underneath the antenna zone.
Routing Gates Before Autoroute
Before routing starts, enforce these rules:
- USB_DP / USB_DM: route as Top-layer differential pair first, J1 -> D1 -> U1, no vias if possible, 5 mil length match.
- SPI nets to J2/J6: route with continuous L2 GND reference; avoid crossing L3 split boundaries.
- I2S nets: keep short between U1 and U4, maintain spacing, avoid unnecessary vias.
- Power: wide pours/traces, star from U2 3V3 to U1, U4, J2, J6; VBAT and VBUS kept wide and short.
- Avoid 90-degree/acute traces; use 135-degree/arc corners.
- Add GND stitching vias near any high-speed/medium-speed layer transitions.
Recommendation
Do not autoroute the board in its current placement. First perform a targeted re-placement pass to correct the critical violations above, then clear stale routing if needed, then route USB first, power second, and remaining signals afterward under the declared constraints.
Scope
Current Board State
Summary Verdict
Pass / Fail Matrix
Critical Placement Violations To Fix Before Routing
Routing Gates Before Autoroute
Recommendation
