Temperature and Humidity Sensor Node Design
Thought for 3 sec
Work done
- Reconfigured the PCB to a Standard 2 Layer stackup while preserving the 50 mm × 50 mm board and 2 mm rounded corners.
- Set the routing intent to top copper for signal/power and bottom copper as the primary reference/plane layer.
- Re-placed the board for the 2-layer strategy: J1 at the left edge, U1 at the top antenna edge, U2 away from the power cluster, and D1/U3/U4 near USB-C input.
- Updated the Implementation Notes with the 2-layer stackup, placement strategy, verification status, and remaining work.
- ✅ 2-layer stackup is configured and board dimensions are retained.
- ✅ Component placement is optimized for USB-C access, ESP32 antenna position, power-path compactness, and sensor thermal separation.
- ❌ Routing is not fabrication-ready yet: the latest check still reports 49 airwires, meaning copper routing remains incomplete.
- ❌ Final fabrication readiness is blocked until routing is completed and the airwire check is clean.
Complete PCB routing next, prioritizing USB D+/D−, VBUS/5V, 3V3, GND, and I2C, then re-run checks before export/manufacturing.
Route remaining nets
Run DRC check
Review placement bottlenecks
Add stitching vias
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Implementation Notes
Selected Architecture
- USB-C 5 V default sink input using J1 with 5.1 kΩ Rd pull-downs on CC1/CC2.
- VBUS input is protected by D1 TVS/ESD and U3 TPS25940 eFuse stage.
- U3 protection is configured with:
- R5 = 89 kΩ for approximately 1 A current limit.
- R6 = 453 kΩ, R7 = 27.8 kΩ, R8 = 100 kΩ divider targeting approximately 4.5 V UVLO rising and 5.75 V OVP.
- Protected 5 V feeds U4 AP2112K-3.3TRG1 LDO.
- 3V3 rail powers U1 ESP32-S3-WROOM-1-N16R8 and U2 SHTC3.
- U2 uses I2C on ESP32 pins IO8=SDA and IO9=SCL with 4.7 kΩ pull-ups.
- USB D-/D+ are routed in the schematic to ESP32-S3 IO19/IO20 for native USB Serial/JTAG.
Layout Setup
- Board size remains 50 mm × 50 mm, rounded rectangle, 2 mm corner radius.
- Stackup has been changed from 4-layer to Standard 2 Layer.
- Top copper is configured for signal and power routing.
- Bottom copper is configured as the primary power-plane/reference layer, intended to be used as the main GND plane during routing.
- J1 is placed at the left board edge for cable access and short USB entry path.
- U1 is placed at the top edge with antenna-facing edge placement/keepout intent.
- D1, U3, U4, and related power passives are grouped near the USB-C input to minimize protection and regulator loop lengths.
- U2 SHTC3 is placed in the lower-right region, away from the eFuse/regulator heat sources.
- I2C pull-ups R3/R4 are positioned near the sensor-side I2C route.
2-Layer Routing Strategy
- Route USB D+/D- as short, direct, top-layer traces between J1 and U1 where possible.
- Avoid cutting the bottom GND reference under USB and ESP32 RF return-current paths.
- Route VBUS_IN, 5V_PROT, and 3V3 with wider traces or pours on top copper; use short GND stitching vias near power input/protection/regulator capacitors.
- Keep the ESP32 antenna region free of copper and routing as much as the tool/manual routing flow allows.
- Keep I2C SDA/SCL on top layer with short paths to U2; avoid routing them through the power cluster.
Verification Status
- Direct layout verification confirms the board is 50 mm × 50 mm with 2 mm rounded corners and a 2-copper-layer stackup.
- Stackup verification confirms Top Copper = Signal and Bottom Copper = Power Plane.
- All 24 layout components remain on the top side.
- Placement verification reports no overlap/out-of-board issues from the placement pass.
- Design review still reports 49 airwire errors because board copper routing is not complete after the 2-layer conversion and re-placement.
- No missing-footprint, invalid-layer, overlapping-copper, overlapping-trace, dangling-trace, or floating-copper warnings were returned in the latest filtered review result; the blocking physical issue is unrouted nets.
Remaining Work
- Complete copper routing for all board nets, especially VBUS/5V, 3V3, GND, USB D+/D-, and I2C.
- Re-run design review after routing to confirm airwires are cleared.
- Validate USB D+/D- routing visually for short length, close pairing, and uninterrupted ground reference.
- Verify the ESP32 antenna keepout and bottom-plane clearance around the RF antenna before fabrication.
- Replace generic passives with production MPNs if required for final procurement.
- Consider adding mounting holes after enclosure requirements are known.
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