Schematic Capture Plan
Stop State — 28 October 2026
Execution stopped because the account ran out of ACUs. Schematic is incomplete and not electrically approved. No PCB layout was requested or performed. Resume by reading actual current schematic and fresh ERC; do not trust earlier counts as current. Last directly inspected snapshot was 135 components / 172 nets; later capture added some parts, but final state was not inspected before tools became unavailable. The last capture result was incomplete text, not a reliable completion report.
Scope and Requirements
See Project Specification (slug project-specification, short ID 3f) for confirmed requirements. Work is schematic first only. Future 160 × 100 mm envelope is provisional. No memory capacity or technology substitution is approved. No surge test levels agreed. LCSC preferred.
Captured at Last Direct Inspection
14 groups: input header, LTC4364 input protection, INA236 sensing, always-on TPS7B8633 LDO, MAX9015 ignition logic, TPS54360B 5 V buck, MCP2515 Classical CAN controller and ISOW1044 generated isolated 5 V/transceiver, two SP3232E RS232 channels, CAT24C32 EEPROM, PCF2131 RTC/coin cell, four RGB LEDs with separate TCA9555, four TCA9555 for 64 independent 1.8 V GPIO and PCA9306 translator. Captured does not mean correct or validated. No visible schematic-wire drafting completed by the first pass. Supply rails and functional groups were labelled.
Critical Review Findings — Fix Status Unconfirmed
Independent read-only review found these concrete defects. Fix instructions were issued, but no reliable final evidence was returned; assume OPEN until current netlist proves otherwise:
- Input MOSFET gates/topology swapped: HGATE-controlled MOSFET drain must connect to VBAT_IN, DGATE-controlled drain to SENSE, common sources SOURCE. Snapshot Q1 DGATE drain was VBAT_IN and Q2 HGATE drain SENSE. In this arrangement OV cutoff/current limiting can be bypassed by body diode. At 50 V, downstream LDO (42 V absolute max) and monitor (48 V) are at risk.
- Gate Zeners reversed: verify Diodes BZX84C15 pin diagram, then cathode to gate, anode to SOURCE. Snapshot pins 1 on gate/3 SOURCE appeared wrong.
- Restart circuit can hiccup indefinitely: R15 1 MΩ/C10 470 nF/Q4/Q5 timer does not reset cleanly. Do not call nominal 170 ms a verified restart function. Use verified supervisor/latch with minimum off-time and safe PMIC sequence, or leave explicitly incomplete.
- L1 generic 0603 is invalid for multiamp buck: select genuine shielded 10 µH part with adequate saturation, provisionally ≥7 A for maximum current-limit criterion, correct footprint/rating.
- UVOV thresholds have tolerance/hysteresis: approximate snapshot OV 35.0–36.8 V, UV falling 6.32–6.63 V, UV rising up to 7.05 V. User asked 6.5/36 V. Do not silently retarget to 6.2/37.5 V. Establish allowed tolerance or precision solution.
- LTC4364 output bulk capacitor recommendation not met by initial ceramics. Verify datasheet and add correct low-ESR bulk; 47 µF/63 V suggested. Check ceramic-to-bulk constraint.
- Gate buck start with LTC4364 ENOUT so load does not start during pass-FET ramp. Check CSD19532Q5B SOA and fault timer; C1 47 nF, C3 10 nF provisional.
- Upstream fuse needed before input TVS; otherwise shorted TVS is not protected by downstream limiter. Verify input connector rating.
- LEDs powered by 5 V can backfeed unpowered 3.3 V expander. Move LED supply to 3.3 V with recalculated resistors and verified common-anode pinout, or switch supply safely.
- Ignition BAT54C reverse rating only 30 V. Use appropriately rated low-leakage diode; verify clamp leakage and thresholds. Nominal prior thresholds 3.18 V rising/2.76 V falling are not exact 3 V.
- SOC_PWR_HOLD and RS232 need compatible SoC bank voltage. SP3232E VIH minimum 2 V, outputs 3.3 V; cannot directly use 1.8 V pads. Use 3.3 V bank or translators. Set flying caps ≥16 V.
- INPUT_FAULT_N pullup to always-on rail can backfeed off SoC; change interface/pullup appropriately.
- CAN protection: add appropriate TVS to isolated ground and selectable/DNP termination. Common-mode choke is a design option, not automatically required.
Outstanding Subsystems
After initial capture, processor, PMIC, DDR4, eMMC, Ethernet, USB, Murata wireless, SD/boot/debug were outstanding. Subsequent review saw U50/U51/U60 additions but excluded them; do not infer completion. Last capture reply was only 'Now Molex headers alone.' Inspect their actual identities/connections and finish every required block or record a specific per-block blocker.
Memory and PMIC blockers
- DDR4: initial library search found no discrete verified part. Candidate two Micron 16 Gbit x16 devices for 4 GB total. MT40A1G16TB-062E IT:F proposed, but exact current manufacturer ordering status/package must be verified. Older KD/RC variants reported obsolete; don't substitute blindly. Old datasheet https://www.mouser.com/datasheet/2/671/16Gb_DDR4_SDRAM-1578714.pdf covers KD/RC, NOT TB geometry. Need newer TB manufacturer package source before custom footprint. Seek approval to create missing library parts; no memory-technology change approved.
- NXP hardware guide calls for individual 240 Ω 1% ZQ resistors, SoC DRAM_ZN 240 Ω, reset pull-down; reverify exact pin mapping. DDR4 support at 2400 MT/s does not prove selected 16 Gbit configuration validated by NXP.
- PMIC: PCA9450AA is Mini family direction, not C (Plus) or B (Nano). Initial library did not contain AA. Exact primary datasheet confirmation required. BUCK6 default reportedly 1.1 V vs DDR4 1.2 V; source proper DDR4 configuration/alternate rail solution and 2.5 V VPP, don't assume firmware can fix power-on sequencing. Missing verified part requires custom-part approval or sourced alternative.
- eMMC 256 MB: no exact verified library part located. Larger industrial eMMC requires user approval. Initial alternatives: 4 GB EMMC04G-M627-A01 lacked datasheet; 16 GB MKEMF016GT1E-IE industrial candidate; 32 GB Samsung candidate rated only −25 °C rejected for temperature. Do not confuse 256 MB target with 256 Mbit or 256 GB.
Validation State
First report: 10 single-pin-net errors at unconnected SoC boundaries, 5 undriven-net reports, 7 untyped-pin warnings. Later independent review saw >40 floating-pin errors on additions, only first page inspected. No clean ERC demonstrated; no final direct fresh check available. No SPICE simulations performed. Reviewer estimated buck frequency/compensation plausible but min-input full-load behavior, total power margin and MOSFET SOA remain unverified. 1.8 A initial load estimate unsupported; calculate full SoC/4GB DDR4/peripheral demand and 1.5× capacity requirement. USB VBUS total budget 530 mA. No layout DRC approval applicable.
Required Resume Order
- Inspect current schematic and current ERC; reconcile all mutations after 135/172 snapshot.
- Correct critical topology/polarity/restart/rating problems and re-check only those fixes.
- Present custom DDR4/PMIC part creation and eMMC capacity decisions to user, with recommended sourceable alternatives. Keep independent circuits progressing.
- Complete SoC/PMIC/DDR4/storage, USB, Ethernet, wireless, SD/boot/debug and total power budget. Each required item must be complete or have a specific blocker, not just unattempted.
- Independent electrical review and simulations where models support them; record unavailable validation.
- Draft/arrange schematic for user approval only after capture review. No PCB work until explicitly approved.
Primary Architecture References
Internal Continuation References
Current-project capture reference 24 (thread eb74739d-b848-42cd-8a10-73d66b85c60f); review reference b2. Read existing state before resuming or replacing. Review findings were sent to capture, but fixes were not confirmed. Specification short ID 3f; this capture-plan short ID jn. Project description set; user's custom project name retained.