PMIC implementation status
Status
Power block added but NOT approved for fabrication or power-up. Execution stopped at account ACU limit before review fixes. PCB layout and schematic drawing were not changed. Supplier preference is Mouser/DigiKey equally, Arrow or comparable major suppliers acceptable; current manufacturing profile still lists LCSC.
Implemented (build report, not yet independently repaired)
- U31 implemented with PCA9450CHNY library identity and manufacturer part number overridden to PCA9450AAHNY. This is NOT approval to buy a C variant. Resolve dedicated AA library part and audit physical mapping/BOM before release. NXP datasheet https://www.nxp.com/docs/en/data-sheet/PCA9450.pdf .
- L100–L105 Murata DFE201612E-R47M 0.47 uH; C100–C121 support; R100–R105; Y100 32.768 kHz; C130–C181 SoC decoupling.
- PMIC supplies VDD_SOC, VDD_ARM, VDD_GPU_VPU_DRAM, 3V3, 1V8, NVCC_DRAM_1V2, NVCC_SNVS_1V8, VDD_SNVS_0V8, NVCC_SD2, VDDA_1V8 and VDD_MIPI_0V9.
- PMIC_ON_REQ, PMIC_STBY_REQ, POR_B, RTC_RESET_B, PMIC_CLK_32K, I2C1 connected. GPIO1_IO09 interrupt; GPIO1_IO02 watchdog; GPIO1_IO04 SD voltage selection.
- Former VDD_PHY_0V8 split: PCI/USB/analogue/ARM PLL 0.8 V to VDD_SOC; DRAM PLL 0.8 V to GPU/VPU/DRAM; MIPI 0.9 V separate. Nine analogue 1.8 V pins moved to VDDA_1V8. 54 previously floating VSS pins connected to GND. RTC_XTALO tied to VDD_SNVS_0V8.
- Full builder asset: https://cdn2.flux.ai/flux-comment-files/files/commentFileId-6a5a2e74c4a3d42ed6911e1eb2b8b0bdcfba637c3d1e1b0ca8cd1792a89a3f48.md?GoogleAccessId=fleet-agent-worker%40graviton-mvp.iam.gserviceaccount.com&Expires=4946796700&Signature=nDIFK5Ikfolg5Zdp%2F2HN%2BG623Ibz1PC1sfcqdTg1fh0xn8WnAaQbig2o3WobxG%2FBu9Vcta2s%2BccvqqFvd%2B0QrM2CxIL%2FE0aykf0ALuZn6FpWxrjN6GWryGsHPuPHrSE7TFc7ZGx%2B%2FM%2FmQVj68dHzysYwg9dIPCdgFKQDp0icR4CoqVGqlPEfdKbqVn79uoRs%2Bo5uA0YdtZZ6b3LvkzNb%2Ful5yWGsJG6H6ZQBIKcENWqrRcRjV1OuR%2F7Xpc6O4%2B4f7LfSciQuRjSGirhsOjjtDTcZq6ec5cAC68vBdAJsAJ7hrpHC5vn4G1QPRR465kcG9kywhe9mvlSbkYYOHAh1UA%3D%3D
Independent review findings (one review round completed; no fixes applied)
- BLOCKER U30 library mapping: pin names and ball IDs swapped on many pins; footprint reportedly 521 pads instead of 486, mixing ball IDs and repeated signal names. Audit/rebuild against https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf before layout. Functional net labels do not prove correct physical mapping.
- DDR4 incomplete: no DRAM devices, no dedicated 2.5 V VPP supply; U30 P2/DRAM_ZN missing verified 240 ohm 1% resistor to GND. U41 is Ethernet supply, not DDR VPP. AA PMIC BUCK6 starts at 1.1 V, while reviewer verified DDR4 NVCC_DRAM range 1.14–1.26 V; SPL must configure 1.2 V before DDR initialisation. Shared MIPI 1.2 V rail also below range at startup. Need resolve startup compliance, not assume firmware makes every startup condition acceptable.
- Upstream U5/L1: 5 V budget remains unverified. Builder estimated 4–4.5 A total, reviewer ~3.3 A, both estimate-based vs U5 3.5 A claim. Do not use either as confirmed demand. Recalculate with sourced processor/peripheral maxima, efficiency and operating modes; resize U5/compensation/support if needed. L1 generic 10 uH/6 A on 0603 footprint invalid; select real inductor with temperature-dependent saturation rating.
- R57 GPIO_EXP_INT_N: 1.8 V pull-up into GPIO1 3.3 V bank; reviewer recommends pull-up to 3V3, after verifying expander INT maximum voltage. Threshold used in review unverified.
- L100–L103: reported 5.5 A saturation at 20 C vs 5 A max PMIC limit, insufficient temperature margin; select suitable hot-rated inductors. L104–L105 less constrained at 4 A max limit.
- U31 library C identity / AA MPN override remains unresolved procurement hazard. Create verified PCA9450AAHNY part, don't order C.
- Boot straps BOOT_MODE0/1 floating; TSENSOR_RES_EXT needs investigation. Peripheral missing-power errors remain on U40/U41/U42/U50/U51/U60 outside PMIC build scope.
Review-confirmed points
Reviewer reported PMIC I2C/ON_REQ/STBY_REQ/SD_VSEL allow 3.3 V signalling; do not move whole processor banks to 1.8 V without need. Feedback/sense mapping and SNVS/core/IO sequence reported correct. POR_B pull-up to NVCC_SNVS_1V8, RTC external-clock tie, SD_VSEL pull-low and VINT 1 uF reported correct. WDOG reset disabled by default; firmware WDOG_B_CFG = 0b11 for cold reset. PMIC LDO dissipation roughly 0.5 W estimate; thermal review needed. Y100 load capacitor tuning needed. PMIC_RST_B test pad recommended. SNVS loses supply when 5V_SYS off; external RTC covers timekeeping.
Decisions to put to user
- Recommended: replace U31's relabelled C library identity with a dedicated verified PCA9450AAHNY part while retaining reference circuit; do not accept procurement of PCA9450CHNY.
- Recommended: retain specified DDR4 and add memory devices, DRAM_ZN 240 ohm resistor, sequenced VPP 2.5 V and validated pre-DDR BUCK6 1.2 V setup. Alternative: migrate memory architecture to LPDDR4 to match factory 1.1 V reference. DDR change affects memory bus and power/firmware.
Resume
Build reference 9l; review reference gf (review report delivered but tool result text truncated at end). Retrieve full persisted review if available. No second independent review round needed: steer builder for focused fixes and verify changed objects/checks directly. Resolve PMIC part creation and U30 part defect; do not treat present circuit as manufacturing-ready. Record sources/capacitor DC bias/current ratings and final demand margins. Todos at stop: implementation captured; independent review performed, findings unresolved. No claim of a functioning whole board is justified.