High-Voltage Piezo Amplifier Design

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2/3 Build the supported amplifier, power-supply, filtering, and protection schematic.

Set provisional noise targets and independently check the regenerative amplifier architecture.

Build the supported amplifier, power-supply, filtering, and protection schematic.

Verify connectivity, ratings, and simulations; document any remaining blockers.

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"Provisional Piezo Driver Schematic" completed.

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I recorded provisional prototype targets of 5 mV RMS output noise, 20 mV peak-to-peak switching ripple, and 0.1% THD in the Specification. These are design goals—not achieved results or guaranteed microscope resolution.
I checked the regenerative architecture and started schematic capture. Your project now contains 28 components and 18 nets, including an auxiliary regulator and passive circuitry, but it is not yet a complete or verified high-voltage piezo driver.
Remaining work includes:
  • Completing the regenerative power stage, bus supply, filtering, and control loop.
  • Verifying current limits, returned-energy handling, temperature shutdown, and safe discharge.
  • Checking connectivity and simulating stability, ripple, and continuous-operation losses before layout or hardware testing.
Do not connect the actuator or apply high voltage to this unfinished design. Execution stopped because your ACUs ran out.

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Specification
Project Overview
  • Status: Draft; feasibility and architecture not approved.
  • Design a high-voltage amplifier and its power supply for a microscope scanning-probe stage using the PiezoDrive SA050520 actuator.
  • No schematic or PCB has been built.
Intended Use
  • Laboratory microscope scanning stage.
  • Single actuator channel is the initial scope.
  • Continuous operation at 0–100 V, 10 kHz is required; burst-only current ratings are not acceptable.
What the Device Should Do
  • Produce a sinusoidal voltage across the actuator: V(t) = 50 V + 50 V sin(2π × 10,000 Hz × t).
  • Target range: 0–100 V, frequency: 10 kHz.
  • Source and sink capacitive current without oscillation, clipping, or unsafe startup/shutdown excursions.
  • Provisional prototype goals: residual output noise ≤5 mV RMS integrated over 0.1 Hz–100 kHz, excluding the commanded sinusoid and deterministic harmonics; carrier ripple ≤20 mVpp at the actuator terminals with a 20 MHz measurement bandwidth. These are engineering targets, not validated microscope-resolution requirements or achieved results.
  • A separate provisional sinusoidal tracking/distortion goal is ≤0.1% THD at the intended load; gain/phase calibration and endpoint behavior remain to be qualified.
Main Features
  • High-voltage output and included power supply.
  • Current limiting, thermal protection, controlled startup/shutdown, and actuator discharge are required design features, not yet implemented.
Mechanical System Architecture
  • Actuator is an off-board stack mounted in the user's stage.
  • Mechanical flow: stack → stage flexure/moving mass → scanning probe.
  • Mounted-stage resonance, moving mass, preload, cooling, and amplifier packaging are not yet specified.
  • Manufacturer lists 74 kHz actuator resonance; this is not a guarantee of the assembled stage bandwidth or safe continuous full-amplitude operation.
Electrical System Architecture
  • Functional flow: waveform command → protected high-voltage source/sink amplifier → actuator.
  • Power flow: external source → included power supply → amplifier rails.
  • User selected an energy-recovering switching amplifier. Development direction: synchronous regenerative half-bridge, multistage damped output filter, signed-current feedback/protection, and actuator-terminal voltage feedback.
  • Include an isolated external low-voltage source, boost bus supply, bulk energy buffer, bus overvoltage dump, and fail-safe actuator discharge. Returned energy must not rely on an ordinary boost regulator being able to sink current.
  • Architecture review gives conditional development approval only: filter/control stability, PWM timing, continuous losses and fault energy paths must be qualified before a complete schematic is claimed.
Hardware Subsystems
  • Amplifier: stable with effective piezo capacitance and wiring parasitics; bidirectional output current required.
  • Power supply: rail voltages, input source, power rating, and returned-energy handling to be determined from selected amplifier topology.
  • Protection: output current limit, temperature sensing, safe discharge, and output-voltage limits.
  • Actuator: exact SA050520; do not substitute on the assumption that it is a 1 µF load.
Interfaces and Connections
  • Waveform-command input amplitude/source and connector are unresolved.
  • Default prototype command interface: external 0–5 V analog input mapped to 0–100 V output, with startup ramp and default-disabled enable. This is an agent-selected assumption, not a user-provided interface specification.
  • Piezo output wiring and grounding are unresolved.
  • Power-source interface is unresolved; prefer a certified isolated external low-voltage supply over a custom mains front end for the first prototype, subject to power feasibility.
Power and Runtime Expectations
  • The user authorizes inclusion of a power supply.
  • Continuous 10 kHz, 100 Vpp operation is confirmed.
  • No runtime, efficiency, or cooling target is approved yet.
  • Use a certified isolated external 48 V supply as the prototype input direction; its exact rating is pending the completed loss budget. Nominal high-voltage bus near 120 V is provisional and may change to satisfy headroom and PWM timing.
Power Tree and Power Budget
  • No supply rails are selected; the following is load-current sizing, not a DC supply power budget.
  • Ideal capacitive current: i = C dV/dt; I_peak = 2π f C V_peak.
  • At 10 kHz and 50 V peak with the originally stated 1 µF: 3.14 A peak, 2.22 A RMS.
  • At the manufacturer's 1.8 µF small-signal nominal value: 5.65 A peak, 4.00 A RMS.
  • A 3.6 µF effective-capacitance scenario requires 11.31 A peak, 8.00 A RMS. This is a preliminary sizing scenario, not a measured value at this drive and not a guaranteed worst case.
  • A 4.32 µF scenario (1.8 µF × 1.20 tolerance factor × 2 effective-capacitance factor) requires 13.57 A peak, 9.60 A RMS. This does not include all temperature growth and is not a guaranteed worst case.
  • A provisional amplifier capability target is approximately 20 A peak, 14 A RMS for continuous repetitive operation; this remains subject to load characterization, thermal protection, and topology review, not just absolute-maximum or pulse ratings.
  • Required sine-wave voltage slew rate: 3.14 V/µs; design needs margin.
  • Reactive load current is not equal to real DC input power. Driver losses, dielectric losses, returned-energy handling, and mechanical loading must be evaluated separately.
Manufacturing and Assembly Expectations
  • Prototype first; PCB stackup, assembly vendor, footprints, and manufacturing files are not selected.
  • Provide voltage/current/temperature test access once the circuit is selected.
Firmware-Relevant Hardware Requirements
  • No embedded controller or firmware is required by the user so far; waveform-generation source remains open.
Physical Design Expectations
  • High-voltage insulation, guarded terminals, heat sinking, and safe handling are required.
  • Board envelope and enclosure remain open pending thermal design.
Important Design Decisions
  • Use 0–100 V unipolar operation rather than ±50 V.
  • Include a power supply in the design.
  • Correct the load assumption using the named actuator's published capacitance before selecting current capability.
  • Use continuous RMS and thermal ratings, rather than pulse-current specifications, to qualify the output stage.
Source Findings
  • PiezoDrive product page lists SA050520 capacitance as 1.8 µF and voltage range as −30 to +150 V; 0–100 V is within the published voltage range.
  • PiezoDrive SA-series specification page lists capacitance tolerance ±20% and actuator resonance 74 kHz. It explains that the listed capacitance is small-signal and effective capacitance increases with drive amplitude and temperature, reaching approximately twice small-signal capacitance at full range. Full range is not the same as this 100 Vpp requirement.
  • These are manufacturer website specifications, not a separately verified PDF datasheet. No separate SA050520 PDF datasheet was identified.
  • Mounted-stage resonance and allowable continuous operation at this drive remain unverified.
  • Architecture check requires including the 1.44 µF low-tolerance case in ripple and stability verification, plus 1.8, 3.6, and 4.32 µF, open load, and extended-capacitance faults.
Assumptions
  • Single-channel voltage drive; no closed-loop position control specified.
  • Values calculated above assume a purely capacitive load below relevant mechanical resonances; actual impedance must be measured on the mounted actuator.
  • Continuous operation is a user-confirmed requirement, not an assumption.
  • User has no noise specification or intended imaging resolution; the provisional electrical noise targets above enable prototype development without claiming imaging performance.
  • Provisional piezo-temperature trip is 70°C with sensor open/short detection and a latched fault; this is below the published 85°C ceiling but is not a validated internal-temperature or mechanical safety envelope.
Change Notes
  • User clarified 100 V means peak-to-peak and the waveform is sinusoidal.
  • User approved a 0–100 V swing, identified SA050520, and authorized a power supply.
  • Manufacturer lookup changed nominal capacitance from the initial 1 µF assumption to 1.8 µF; final current rating remains open pending effective-capacitance and temperature assessment.
  • User confirmed continuous operation and authorized the manufacturer's capacitance as the design basis.
  • Architecture feasibility calculations and candidate-screening evidence are saved separately in Continuous Drive Feasibility.
  • User chose the switching architecture and confirmed no noise/resolution specification is available; provisional electrical goals and the architecture-review caveats were recorded before prototype capture.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • Mechanical System Architecture

  • Electrical System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Source Findings

  • Assumptions

  • Change Notes