Rocket OBC Design
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Project Specification
Project Specification
Project Overview
Rocket payload onboard computer (OBC), status: Draft/Review. The board accepts regulated 3.3 V and hosts an ESP32-S3 development module, navigation/environment sensors, GPS, CAN payload networking, and a buzzer driver.
Intended Use
Prototype rocket payload OBC installed on the existing 89.6 mm circular PCB with three existing mounting holes.
What the Device Should Do
- Operate the Heltec WiFi Kit 32 V3 at 3.3 V logic.
- Read MPU6050, BMP280, and GY-271-compatible modules over one shared I2C bus.
- Receive NMEA GPS data over UART and support GPS configuration transmit.
- Interface the MCU TWAI/CAN controller to an external HiLetgo SN65HVD230 module.
- Distribute CAN and selected low-current 3.3 V/control signals through payload FFC con...
Power Budget
Power Budget
Scope
3.3 V OBC rail only. Excludes the 24 external payload boards and any high-current load beyond the FFC boundary.
Input and Protection Sizing
- Upstream regulated 3.3 V source recommendation: at least 1.0 A continuous capability with low transient impedance; 1.5 A preferred margin.
- Input connector and fuse/protection path: target ≥1 A continuous without excessive voltage drop.
- Local energy storage: 10 uF bulk plus 100 nF high-frequency bypass at input, with additional local decoupling per external module interface.
- Because the source is already 3.3 V, series protection must have low resistance; excessive fuse/PTC drop can violate ESP32 brownout margin.
The FFC 3.3 V pins are auxiliary low-current distribution only. This budget do...
Firmware Getting Started
Firmware Getting Started
Final GPIO assignments will be populated from the completed schematic. Target framework: ESP-IDF with Heltec WiFi Kit 32 V3 board support.
Required peripherals
- I2C master: MPU6050, BMP280, GY-271-compatible module interfaces.
- GPIO interrupt: MPU6050 INT.
- UART: GPS RX/TX crossed at the connector.
- TWAI: CAN TX/RX to external SN65HVD230 module.
- GPIO output: buzzer MOSFET gate.
- Configure safe GPIO defaults; keep buzzer off.
- Initialize I2C and probe expected addresses.
- Configure IMU interrupt input.
- Initialize GPS UART.
- Initialize TWAI at the mission bus bit rate; termination is external.
- Start sensor acquisition and telemetry tasks.
Built and verified the complete Rocket Payload OBC schematic. It includes the 3.3 V input protection, WiFi Kit 32 V3 interface, MPU6050/BMP280/GY-271, NEO-6M GPS, SN65HVD230 CAN interface, four active FFC ports plus one DNP port, and MOSFET-driven buzzer. Final ERC review reports no open warnings or errors.
Open items
- Library uses 10051922-1210EHLF, not the requested 10051922-1210ELF; contact orientation and footprint must be corrected before manufacturing.
- Modules are represented by verified headers because exact breakout-board parts were unavailable.
- PCB components are not placed; some footprints remain outside the circular outline.
- Further execution is paused because no ACUs remain.
Suggested next steps
- Import/create the exact
10051922-1210ELFconnector. - Review the schematic and documented FFC pinout.
- Place components on the circular PCB.
- Configure CAN/power trace rules, then route and run DRC.
Fix FFC connector
Review FFC pinout
Place components
Check ERC/DRC
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Project Specification
Project Overview
Rocket payload onboard computer (OBC), status: Draft/Review. The board accepts regulated 3.3 V and hosts an ESP32-S3 development module, navigation/environment sensors, GPS, CAN payload networking, and a buzzer driver.
Intended Use
Prototype rocket payload OBC installed on the existing 89.6 mm circular PCB with three existing mounting holes.
What the Device Should Do
- Operate the Heltec WiFi Kit 32 V3 at 3.3 V logic.
- Read MPU6050, BMP280, and GY-271-compatible modules over one shared I2C bus.
- Receive NMEA GPS data over UART and support GPS configuration transmit.
- Interface the MCU TWAI/CAN controller to an external HiLetgo SN65HVD230 module.
- Distribute CAN and selected low-current 3.3 V/control signals through payload FFC connectors.
- Drive a buzzer through a protected low-side MOSFET stage.
Main Features
ESP32-S3 OBC; shared I2C sensors; UART GPS; 3.3 V CAN transceiver-module interface; four populated 12-pin FFC payload ports plus one optional DNP port; buzzer output.
System Architecture
See the Block Diagram project file.
Hardware Subsystems
- Power input: external regulated 3.3 V only; fuse/protection; 10 uF bulk and 100 nF bypass; no onboard regulator.
- Compute: Heltec WiFi Kit 32 V3 development module.
- Sensors: external MPU6050, BMP280, and GY-271 module interfaces.
- GPS: external GY-NEO6MV2 / NEO-6M module interface.
- CAN: external SN65HVD230 module interface; no onboard 120 Ω termination.
- Payload: Amphenol ICC 10051922-1210ELF FFC connectors.
- Alert: MCU-controlled NMOS low-side buzzer stage.
Interfaces and Connections
3V3/GND power; I2C SDA/SCL and IMU interrupt; crossed UART TX/RX; CAN controller TX/RX to CTX/CRX; CANH/CANL shared by payload connectors.
Power and Runtime Expectations
The upstream adjustable buck module supplies regulated 3.3 V. OBC electronics and attached local modules are budgeted; 24 external payload nodes are explicitly excluded.
Power Tree and Power Budget
External 3.3 V → protection → local 3V3 rail → OBC module, sensors, GPS, CAN module, buzzer. Detailed assumptions are in the Power Budget project file.
Manufacturing and Assembly Expectations
Compact SMD assembly. Preserve the existing circular outline and mounting holes. Exact FFC connector MPN is mandatory.
Firmware-Relevant Hardware Requirements
GPIO mapping must support one I2C peripheral, one UART, TWAI/CAN TX/RX, IMU interrupt, and buzzer GPIO. Final assignments are recorded in Firmware Getting Started.
Physical Design Expectations
Do not modify the existing 89.6 mm circular PCB or its three mounting holes. Schematic construction only in this phase.
Important Design Decisions
No onboard regulator; no onboard CAN termination; external module interfaces are acceptable when exact breakout modules are unavailable; payload boards are external and not represented as local ESP32-C3 nodes.
Assumptions
FFC-distributed 3.3 V is for low-current payload/interface use only and is not rated to power all 24 payload nodes. Breakout-board onboard pull-ups must be removed/disabled if they would parallel the OBC's single pull-up pair.
Change Notes
Initial confirmed architecture captured from user brief and uploaded KiCad PDF baseline. Final schematic uses verified connector interfaces for the unavailable Heltec and sensor/GPS/CAN breakout parts. Four FFC ports are populated and the fifth is DNP. GPIO assignments are recorded in Firmware Getting Started.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
