Top Side PCB Layout

Thought for 3 mins 11 sec
Thought for 5 sec
Searching tasks in /ryanf/solar-usb-c-1s-power-manager-test-testroledecoupling-7ef8~9fx…
Thought for 7 sec — Evaluating review process
2/4 Independently review placement constraints and power-stage geometry

Place all 110 components on the top side within the confirmed 50 × 60 mm outline

Independently review placement constraints and power-stage geometry

Correct unauthorized L6 substitution and resolve blocking U2 placement findings

Verify top-side-only placement, bounds, overlaps, keepouts, and DRC

Thought for 10 sec
Awaiting 1 task
"PCB Placement Review" completed.
Thought for 23 mins 46 sec
Thought for 7 sec
Managing 1 task
Thought for 12 sec — Fixing issues in the builder
3/4 Correct unauthorized L6 substitution and resolve blocking U2 placement findings

Place all 110 components on the top side within the confirmed 50 × 60 mm outline

Independently review placement constraints and power-stage geometry

Correct unauthorized L6 substitution and resolve blocking U2 placement findings

Verify top-side-only placement, bounds, overlaps, keepouts, and DRC

Thought for 11 sec
Thought for 8 sec
Awaiting 1 task
"PCB Placement Validation" completed.

flux

Placed all 110 components on the Top side of the 50 × 60 mm board. Verification shows zero overlaps, keepout/boundary violations, pad-access errors, or required power-stage errors; L6 was restored to the original Coilcraft XAL3225-102ME.
Open items
  • 10 non-blocking switching-stage advisories remain, mainly capacitor-bank alignment and minor routing detours.
Suggested next steps
  1. Clean up the remaining placement advisories.
  2. Route the power stages and board.
  3. Run final DRC and silkscreen cleanup.
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Files

Schematic

Layout

3D View

Project Specification
Status
  • PCB mechanical requirement revised 2026-09-14: exactly 50 × 60 mm rectangular outline, preserving the existing four-layer stackup, with all 110 components on Top and none on Bottom. This supersedes earlier board sizes and the previous permission for two-sided small-passive placement. Edge connectors, SW1, LEDs and other mechanical parts remain accessible. Bulk routing is a separate lead-agent step.
  • Safety-critical schematic rebuild completed; independent M-01…M-16 audit completed.
  • Current schematic: 110 components and 70 nets.
  • Fresh ERC has no open warnings or errors as of 2026-09-04.
  • PCB placement/routing is stale after component replacement and is not fabrication-ready.
Function
Autonomous power manager for a protected 1S Li-ion pack, powered by USB-C or a nominal 6 V solar panel. USB is preferred, solar is secondary, and the charger/system power path allows input-powered loads, battery supplement and battery-only operation.
Implemented Architecture
  1. USB-C input with independent 5.1 kΩ CC pull-downs, connector-side TVS, capacitance and TPS259480 active eFuse programmed at a characterized 1.75/1.99/2.25 A threshold.
  2. Solar input with SMBJ8.0A-13-F TVS and TPS2121 solar OV supervision.
  3. TPS2121 source mux with a 44.2 kΩ ILM resistor and corrected PR1 divider (255 kΩ/100 kΩ) that retains USB priority through the stated 4.00 V minimum input, plus USB/solar OV dividers and ST tied to GND.
  4. MP2617BGL-P 1S switching NVDC charger: ~1 A charge, ~1.37 A nominal input limit with calculated high corner near 1.50 A, VLIM ~5.68 V, pack NTC, termination/recharge, SYS priority/supplement and ACOK/CHGOK.
  5. TPS259535 system UVLO between charger SYS and downstream SYS_BAT, using a 196 kΩ/100 kΩ divider and 10 nF DVDT capacitor for a nominal ~3.26 V falling cutoff and controlled inrush.
  6. TPS63070 always-on 3.3 V followed by TPS259535 protection set near 0.64 A.
  7. Independent 5 V TPS63070 and 12 V TPS61088 AUX converters, selected by center-off SW1 and isolated by separate reverse-blocking TPS259480 eFuses before AUX_OUT.
  8. CHARGE indicator from CHGOK; the green indicator means input-valid / not-charging and is not a unique FULL-state decoder because CHGOK can release or blink during non-full conditions and faults.
Electrical Targets

Table

FunctionTarget / implementation
USB source5 V, 1.5 A continuous guaranteed
Solar basisVmp 5.71 V, Voc 6.94 V nominal, Imp 1.67 A
BatteryProtected 1S, 3.0–4.2 V, >=3 A discharge
Charge current~1 A nominal
Charger input limit~1.37 A nominal; calculated ~1.25–1.50 A tolerance range
Solar VLIM~5.68 V fixed-voltage regulation
System UVLO~3.2 V nominal
3.3 V output500 mA, protection ~0.64 A nominal
AUX 5 V500 mA, isolation eFuse ~1 A nominal
AUX 12 V100 mA, isolation eFuse ~1 A nominal
Acceptance / Remaining Gates
See M-01 to M-16 Independent Audit and M1-M19 Verification Build Report for the full matrices. Schematic/ERC completion does not authorize fabrication. Required gates include the solar reverse-polarity policy, exact pack-NTC curve and temperature window, USB transient class, panel cold-Voc/transient confirmation, battery fuse policy, PCB placement/routing, and bench validation of source transitions, UVLO, 3.3 V load capability, reverse leakage, thermal performance and TPS61088 stability.

  • Status

  • Function

  • Implemented Architecture

  • Electrical Targets

  • Acceptance / Remaining Gates