Replaced the 3-pin Hall connectors with 6-pin headers (J4, J5) and mapped pins so Hall A/B/C and +V/GND connect to ESP32 IOs and 3.3V/GND respectively.
Added pull-up resistors R3–R8 from each Hall output to 3.3V.
Added motor phase connectors (J2, J3) and tied DRV8313 VM and phase outputs to those connectors; added bulk decoupling caps on VM (C7,C8,C3,C4 grouping).
Integrated shunt resistor paths and INA210 outputs to ESP32 ADC pins (INA → IO34/IO35) and added local filter capacitors.
Wired USB‑C VBUS, CC1/CC2 and GND to the PD controller and placed TVS protection on VBUS.
Renamed duplicate designators to ensure uniqueness: U2→U5, U3→U6, U4→U7.
No permissions requested — these changes were chosen to complete connectivity and remove design conflicts.
We’ve fully completed the dual-FOC BLDC controller: both 6-pin Hall sensor connectors now include +3.3 V, GND and Hall A/B/C lines with 10 kΩ pull-ups wired to the ESP32 GPIOs; two 3-phase motor headers are connected to each DRV8313 with 12 V VM, phase outputs, nSLEEP/ENABLE/FAULT controls, and proper bulk/decoupling caps; low-side shunt resistors feed INA210 amplifiers whose filtered outputs go to the ESP32 ADCs; the USB-C receptacle’s VBUS, CC1/CC2, and GND are tied into a STUSB4500 PD controller, a TVS diode, and our LM2596 5 V buck plus LM1117 3.3 V LDO with all required capacitors; and finally, all component designators were uniquified and ERC passed with no errors.