Electrical Verification


do not place just route
Routing requires Agent mode to inspect the updated PCB, check routing feasibility, route all nets, and verify remaining airwires/DRC.
Understood: routing only—no component placement or movement. Switch to Agent mode to route the existing placement and verify all airwires and routing DRC.
Continue in Agent Mode
I’ll preserve the current placement, run a routing feasibility check, route the board, then verify remaining airwires and routing DRC.
Auto-routing converged with the existing placement: all nets are routed. I’m running the final airwire and DRC verification now; no components were moved.
Board routing completed without moving components.
  • 0 airwires
  • 0 dangling traces
  • No routing-related DRC errors or warnings
  • Auto-router noted one skipped decoupling-routing preference on GND, but the net is fully routed and DRC-clean.
Review route quality
Clean up decoupling
Manufacturing readiness
Export fabrication files

Board Bring-Up Plan
Before Power
  1. Confirm no components populate any 12 V converter or traction-voltage circuitry.
  2. Verify C1 polarity and all socket orientations.
  3. Check continuity: +5V-to-GND must not be shorted.
  4. Check isolation: L12V, R12V, +5V, +3V3, and GND must be mutually isolated except for the explicitly shared logic connections.
Initial Power
  1. Remove ESP32, MCP6002, and all AQY212EH devices from sockets.
  2. Apply current-limited regulated 5.0 V at J1.
  3. Measure TP2 = 5.0 V and TP1 = GND; verify no heating.
  4. Install ESP32 only; confirm TP3 approximately 3.3 V.
Analog Test
  1. Install U1 and verify pin 8 = +5 V, pin 4 = GND.
  2. Command 0, 1.0, 2.0, and 3.3 V-equivalent DAC values.
  3. Expected LAMP/RAMP: approximately 0, 1.30, 2.60, and 4.29 V.
  4. Expected LTHR/RTHR: approximately 0, 1.287, 2.574, and 4.248 V.
  5. Fail if either connector-side throttle exceeds 4.4 V at maximum command or does not return low at reset.
Isolated Contact Test
  1. Install one AQY212EH at a time.
  2. With no command, verify open circuit from L12V/R12V to each direction output.
  3. Assert one command and verify only the matching contact closes.
  4. Confirm left commands never affect right contacts and vice versa.
  5. Verify firmware break-before-make behavior for forward/reverse changes.
PS2 Test
  1. Verify J2 pin order before attaching the controller.
  2. Confirm +3V3 and GND polarity.
  3. Probe DAT/CMD/ATT/CLK on TP-accessible logic points or ESP32 pins and confirm communication.
Pass Criteria
  • Stable +5V and +3V3 rails.
  • Throttle outputs match expected transfer and default low.
  • Four contacts default open and switch independently.
  • L12V and R12V remain isolated from each other and all logic rails.
  • Before Power

  • Initial Power

  • Analog Test

  • Isolated Contact Test

  • PS2 Test

  • Pass Criteria