Electrical Verification

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Routing requires Agent mode to inspect the updated PCB, check routing feasibility, route all nets, and verify remaining airwires/DRC.

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Understood: routing only—no component placement or movement. Switch to Agent mode to route the existing placement and verify all airwires and routing DRC.
Continue in Agent Mode

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I’ll preserve the current placement, run a routing feasibility check, route the board, then verify remaining airwires and routing DRC.

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Auto-routing converged with the existing placement: all nets are routed. I’m running the final airwire and DRC verification now; no components were moved.

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Board routing completed without moving components.
  • 0 airwires
  • 0 dangling traces
  • No routing-related DRC errors or warnings
  • Auto-router noted one skipped decoupling-routing preference on GND, but the net is fully routed and DRC-clean.
Review route quality
Clean up decoupling
Manufacturing readiness
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Schematic

Layout

Preview

Project Specification
Project Overview
  • Status: Schematic complete / ready for PCB-layout review.
  • Low-voltage ESP32 carrier for a PS2 controller, dual analog throttle outputs, and four isolated Kelly direction contacts.
  • No traction voltage, motor phase/hall, Foot_SW, e-stop, 12 V input, or onboard converter circuitry is included.
Intended Use
  • JLCPCB prototype and bench validation platform.
  • External regulated +5 V supply only.
What the Device Should Do
  • Power a removable 30-pin DOIT-style ESP32 DevKit V1 and MCP6002 from +5 V.
  • Interface PS2 DAT/CMD/ATT/CLK through 1 kOhm series resistors, with a 10 kOhm DAT pull-up to +3V3.
  • Generate mirrored 1.30-gain left/right throttle outputs.
  • Provide four normally-open AQY212EH isolated contacts while preserving separate L12V and R12V domains.
Main Features
  • Socketed 30-pin ESP32 DevKit using two 1x15, 2.54 mm female headers.
  • Socketed MCP6002-I/P PDIP-8 and four separately socketed AQY212EH DIP-4 devices.
  • 5.08 mm through-hole screw terminals.
  • Nineteen Keystone 4952 through-hole test loops.
  • Four M3 3.2 mm NPTH mounting holes.
System Architecture
Diagram



  
    
  
  
    
  










GPIO25/26

LTHR/RTHR

GPIO21/22/32/33







Regulated +5 V
ESP32 DevKit
MCP6002
PS2
Series resistors + DAT pull-up
Kelly connectors
4x AQY212EH
Hardware Subsystems
Power
  • J1: pin 1 +5V, pin 2 GND.
  • C1 10 uF / 50 V polarized radial bulk capacitor; C2 100 nF ceramic.
  • U1 pin 8 +5V, pin 4 GND, with C3 100 nF / 25 V local bypass.
PS2
  • J2 pin order: +3V3, GND, DAT_PAD, CMD_PAD, ATT_PAD, CLK_PAD.
  • GPIO mapping: GPIO19 DAT, GPIO23 CMD, GPIO27 ATT, GPIO18 CLK.
Analog Throttle
  • GPIO25 = LDAC_RAW; GPIO26 = RDAC_RAW.
  • MCP6002 non-inverting gain: 1 + 3.0k/10k = 1.30.
  • Connector-side transfer includes 1 kOhm series and 100 kOhm pull-down, giving approximately 1.287 V/V.
  • 1N5231B 5.1 V zener clamps have cathodes at LAMP/RAMP.
Isolated Direction Contacts
  • GPIO21 LF_CMD, GPIO22 LR_CMD, GPIO32 RF_CMD, GPIO33 RR_CMD.
  • Each LED input uses 220 Ohm series resistance and 100 kOhm GPIO pull-down.
  • AQY212EH contact pin 4 is the local L12V/R12V feed; pin 3 is the corresponding direction output.
Interfaces and Connections
  • J1: +5V, GND.
  • J2: +3V3, GND, DAT_PAD, CMD_PAD, ATT_PAD, CLK_PAD.
  • J4: LTHR, GND, L12V, LFWD, LREV.
  • J5: RTHR, GND, R12V, RFWD, RREV.
Power and Runtime Expectations
  • External regulated +5 V source; no battery/runtime requirement.
  • Logic GND is common only to ESP32, MCP6002, PS2, and J4/J5 signal GND.
Power Tree and Power Budget
  • +5V -> ESP32 VIN and MCP6002 VDD.
  • ESP32 +3V3 -> PS2 connector and DAT pull-up.
  • L12V and R12V are externally supplied isolated contact-side nets and are not board power rails.
Manufacturing and Assembly Expectations
  • JLCPCB prototype target; later PCB: 2 layer, 1.6 mm FR-4, 1 oz copper, maximum 127 x 127 mm.
  • Through-hole axial 1/4 W, 1% resistors and through-hole ceramic capacitors.
  • DIP sockets and ESP32 female socket headers are assembly intent and must be included in the final BOM/assembly notes.
Firmware-Relevant Hardware Requirements
  • PS2 GPIOs: 19 DAT, 23 CMD, 27 ATT, 18 CLK.
  • Analog GPIOs: 25 left DAC, 26 right DAC.
  • Direction GPIOs: 21 LF, 22 LR, 32 RF, 33 RR.
  • Firmware must command zero throttle and all direction outputs low during boot, invalid input, or fault.
Physical Design Expectations
  • Public nominal DevKit footprint: 30 pins, 15 per side, 2.54 mm vertical pitch, 25.4 mm row spacing, 1.0 mm drills, 1.8 mm pads.
  • Public board-size references vary; verify the delivered module before fabrication, especially body width, USB overhang, antenna end, and button clearance.
  • Keep the four PhotoMOS contact-side paths physically separated from logic and from the opposite controller's isolated domain.
Important Design Decisions
  • MCP6002-I/P and AQY212EH identities are fixed.
  • Phoenix Contact 1729160 (6-position) and 1702558 (5-position) are used where exact KEFA 5/6-position library parts were unavailable; J1 uses KEFA KF128-5.08-2P-AA.
  • No PCB layout was started in this revision.
Assumptions and Remaining Risk
  • The DOIT DevKit ecosystem has clone-to-clone mechanical variation. The carrier footprint uses public nominal geometry and requires a physical fit check against the user's actual board before ordering.
  • Generic through-hole resistors and C2/C3 currently express value/package/rating but do not have final manufacturer MPNs assigned.
Change Notes
  • Completed the full schematic, test points, mounting holes, socket intent, no-connect markings, ERC, isolation checks, and analog DC simulation.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Power

  • PS2

  • Analog Throttle

  • Isolated Direction Contacts

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions and Remaining Risk

  • Change Notes