Power Distribution Network Review
Thought for 1 min 45 sec
Below is a focused PDN (Power Distribution Network) schematic review based on your current schematic nets and parts. I’ve organized it rail-by-rail, mapping sources to loads, noting decoupling/bulk practices, ground/reference strategy, sequencing/supervision, and basic protection. I also highlight critical gaps flagged by the DRC “Airwires” results, since many power nodes are still not fully wired.
High-level summary
- Primary source/input power: USB-C VBUS via TYPE-C-31-M-12 and BAT60JFILM Schottky, feeding PMIC DA9062-00AM2 and system 3.3 V rail.
- Regulators/References:
- PMIC DA9062-00AM2: Buck1/Buck2/Buck3/Buck4 and LDOs, plus reference pins (VREF, IREF) and power-good/enable pins.
- Precision reference + buffer for ADC VREF: REF3140AQDBZRQ1 feeding OPA350UA, creating Net 3 VREF = 4.096 V.
- Major loads:
- STM32F745VEH6: VDD, VDDA, VDDUSB, VCAPs, I/O pullups.
- ICE40UP5K-UWG30ITR1K: VCC, VCCPLL, VCCIO rails.
- DDC232CKZXGT X-ray DAS ADC: AVDD/DVDD, VREF, QGND.
- Peripherals: AT25SL321-UUE-T SPI flash, BME280, USB-C, oscillator ASDM1-10.000MHZ-LC-T, LEDs, etc.
Note on connectivity status
- The DRC shows 222 “Airwires” errors, including many power pins and decouplers. Many observations below are about intent and what’s placed, with recommendations to finish connections and align values/layout to best practices.
Rail-by-rail findings
- USB input / VBUS front-end (Net 25, Net 45, Net 117)
- Source: TYPE-C-31-M-12 VBUS pins to BAT60JFILM (Net 25), providing reverse protection and ORing.
- CC pins: R7, R15 are present; ensure correct values for device role and current advertisement. Airwires indicate incomplete connections to J1 pins.
- Bulk & decoupling: Bulk tantalums are placed (C2, C5, C6, C8 around input nodes). Good start, but ensure ESR/voltage rating and that they sit physically tight at the power-entry and PMIC input.
- ESD/EMI: No dedicated USB ESD diodes on DP/DM detected; consider adding a USB data-line ESD array and a TVS diode for VBUS. A common-mode choke on DP/DM is often used in noisy systems.
- Recommendation:
- Complete J1 wiring (VBUS, CC1/CC2 to Rp/Rd per role, shield and ground stitching).
- Add input TVS (SMBJ5.0A class) on VBUS and an upstream fuse/limiter.
- Ensure D+ / D− have ESD arrays and controlled-impedance routing.
- PMIC core rails (U5 DA9062) Likely rails from U5 mapping (based on nets):
- 1.1 V core (Net 9 via L1 to VCC1V1, feeding ICE40UP5K-UWG30ITR1K VCC and decoupling C45, C46).
- 1.8 V (Net 10 via L2 to VCCINT/AVCC1V8 portals), powering U4 VPP_2V5? and possibly I/O ref nets via LDO2 (Net 20).
- 3.3 V (Net 115 via L4 and L5 filters), feeding U8 VDD/VDDUSB and most 3.3 V loads.
- 1.8 V I/O (Net 40 via L3), feeding U4 SPI_Vccio1, VPP_2V5, plus BME280 VDDIO and U8 VDD/VDDA portals shown on that net; this looks inconsistent (see below). Observations:
- Many DA9062 pins (VLX, VBUCKx, VDD_BUCKx, VBBAT, etc.) have placed inductors and capacitors but numerous incomplete connections per Airwires. Ensure every buck has:
- Correct inductor value/current rating and saturation headroom.
- Input and output capacitors sized per DA9062 datasheet for stability and transient response.
- Short loops and shared grounds via solid planes.
- Net 40 labeling/mapping issue: It carries 1.8 V buck output but also tags U8 VDD, VDDA, and many decouplers. STM32 VDD/VDDA are 3.3 V typical; mixing them on a 1.8 V net is a logical error. This looks like either mislabeled portals or unintended connections. Needs correction before layout.
- Net 18 looks like a 3.3 V digital rail feeding U4 I/O banks, oscillator VDD, and multiple decouplers. Confirm rail intent (name it VCC3V3_DIG) and separate from analog 3.3 V (AVCC3V3) with RC/inductor as needed.
- Recommendations:
- Resolve net intent and naming: separate 3.3 V digital (MCU/FPGA I/O), 3.3 V analog (ADC analog), 1.8 V rails (core or I/O), and 1.1 V core. Rename nets to explicit names and remap portals.
- For each DA9062 buck: finalize L/C values per load and stability tables; place output bulk close to inductor, multiple 0.1 uF/1 uF ceramics near each IC VDD pin cluster.
- Add test points (already a PMIC_TP exists) on each rail for probing and bring-up.
- 3.3 V rail(s) (Net 115, Net 18, AVCC3V3 portals)
- Net 115 includes U8 VDDUSB, U5 VDDIO, BME280 VDD, multiple bulk/decoupling caps, and L4/L5 filters. Likely the main 3.3 V.
- Net 18 shows DVDD for ADC [DDC232], FPGA VCCIO banks, oscillator, and many decouplers. This is also 3.3 V digital by content.
- AVCC3V3 portals feed U1 DVDD and other analog sections through LC and bulk ([C7], [C8], [C41], [C42], [C38] etc.).
- Good practice: isolate analog 3.3 V for ADC with an LC or RC filter from the noisy 3.3 V digital domain; you have inductors [L5] and LC here. Ensure the inductor values and output capacitance meet the ADC PSRR and transient needs.
- Recommendations:
- Consolidate naming to VCC3V3_DIG and AVCC3V3_ANA; verify that U8 VDDA is on the analog-clean 3.3 V rail with its own RC filter per STM32F7 datasheet.
- Confirm total 3.3 V current budget: MCU (worst-case), FPGA I/O, sensors, oscillators, LEDs, plus ADC digital. Validate PMIC Buck capacity with margin.
- Provide local 0.1 uF + 1 uF at each device VDD pin cluster; add 10 uF near rail distribution branches.
- 1.1 V core (Net 9 → VCC1V1)
- Feeds ICE40UP5K-UWG30ITR1K VCC and has multiple local caps ([C45], [C46], [C33], [C34]) shown around U4.
- Recommendation:
- Verify U4 core current draw vs buck rating; ensure minimum output caps and low ESL/ESR ceramic near U4 pins.
- Ensure VCCPLL decoupling ([C33], [C34]) is on the recommended rail (often 1.2 V/1.1 V clean with small RC). Airwires report VCCPLL blocked by auto-layout; ensure this rail is separate from noisy domains and has dedicated local decouplers.
- 1.8 V rails (Net 10, Net 20, Net 40)
- Net 10 appears as a 1.8 V core/logic rail (VCCINT portal), sourced by Buck1 via [L2]; supplies U4 VPP_2V5? and LDO2 branch (Net 20 → AVCC1V8).
- Net 20 shows U5 VLDO2 feeding AVCC1V8; good pattern for a cleaner analog 1.8 V branch.
- Net 40 currently conflates 1.8 V with U8 VDD/VDDA and other nodes: this must be corrected.
- Recommendations:
- Keep analog 1.8 V (if used) on an LDO-filtered branch separate from digital 1.8 V.
- Correct any accidental ties of U8 VDD/VDDA to 1.8 V; STM32F745 VDD/VDDA should be 3.3 V nominal.
- Precision reference and ADC front-end (Net 3 VREF = 4.096 V)
- Chain: REF3140AQDBZRQ1 → OPA350UA buffering VREF to ADC DDC232CKZXGT VREF. Bypass and output caps present ([C3], [C1], [C4], [C5], [C10]) with LC filtering around AV rails feeding this subsystem.
- The ADC also has QGND net separated via portal QGND and tied at U1 QGND pin: excellent. Ensure single-point tie to main GND near ADC per datasheet.
- Recommendations:
- Complete the exact decoupling topology per REF3140 and OPA350 datasheets (input/output caps, any stability constraints at the op-amp output with capacitive load).
- Route VREF as a guarded, quiet trace with Kelvin connection to ADC VREF pin; place local 0.1 uF and 1 uF at the ADC VREF pin to ground (per ADC datasheet).
- Ensure VREF source derives from the analog-clean 3.3 V rail and is not contaminated by digital transients.
- STM32F745 power (U8)
- VDD, VDDA, VDDUSB on nets Net 40, Net 115; VCAP_1/2 with [C53], [C54], [C55], [C63], [C59]-[C62]. Airwires show some VCAP pins are not fully connected to their dedicated caps yet.
- Recommendation:
- Ensure all VCAP pins have the exact capacitance and ESR requirements per STM32F745 datasheet and are wired only to their caps and ground.
- VDDA should have an RC filter from VDD and its own decoupling cluster.
- VDDUSB must be 3.3 V; confirm it’s only on the 3.3 V rail with sufficient local decoupling.
- FPGA power (U4)
- VCC (core) on Net 9 (1.1 V), VCCPLL (Airwires warnings), VCCIO banks on Net 18 and Net 40. Clock/oscillator [ASDM1-10MHz] powered from Net 18; ensure its decoupling caps close.
- Recommendation:
- Match VCCIO levels to interfacing devices (MCU, Flash, ADC digital). If MCU is 3.3 V, most VCCIO should be 3.3 V unless level-shifting is used.
- Isolate VCCPLL with RC and give it dedicated 100 nF close to pins.
- Ensure core rail transient capacity near the FPGA: add multiple 0.1 uF 0402 caps around the device perimeter plus 4.7–10 uF bulk nearby.
- SPI flash and sensor rails
- AT25SL321-UUE-T VCC on Net 40 currently (intended 3.3 V); move it to the proper 3.3 V rail if Net 40 is 1.8 V.
- BME280 VDD on Net 115 (3.3 V), VDDIO on Net 40 (likely 3.3 V too). Keep sensor on the quietest 3.3 V branch you can afford (post-LC if available), with local 100 nF and 1 uF.
- Ground and references
- Single GND net is used widely with some analog discipline: QGND for ADC is separated and tied at U1. USB shield to ground via RC/ESD path indicated ([C17], [R12]).
- Recommendation:
- Confirm single-point connection strategy for QGND to GND and keep analog star-point near ADC reference return.
- Stitch grounds generously around PMIC and high di/dt paths; keep VREF and ADC inputs away from switching current loops.
- USB shield should connect to chassis/earth strategy; if not using chassis, use RC/ESD to signal ground as you’ve started.
- Sequencing, enables, supervision
- DA9062 has many control pins present: ~ONKEY, ~RESET, ~RESETREQ, GPIOs; MCU BOOT0 and NRST nets are present with pull-ups/pull-downs.
- Recommendations:
- Use PMIC power-good rails to gate sensitive loads (e.g., release ADC and FPGA only after rails are in regulation).
- Ensure MCU NRST pull and caps follow datasheet; verify BOOT0 resistor network for intended boot mode.
- Consider adding a rail supervisor on the 3.3 V digital rail if PMIC doesn’t already assert a system-level reset with proper sequencing.
- Protection and EMC
- USB input has Schottky but no upstream fuse or TVS; add polyfuse and VBUS TVS.
- Add ESD diodes on all external connectors (USB D+/D−, CC, any user IO headers like SM06B-SRSS-TB(LF)(SN)).
- Consider common-mode chokes for sensitive clock/USB lines.
- If CT DAS is a noisy environment, consider LC/T filters per rail branches that feed analog domains (ADC, VREF, sensors).
Key issues to resolve next
-
Fix net intent/naming and misconnections:
- Net 40 currently ties 1.8 V nodes and STM32 VDD/VDDA; split and correct.
- Explicitly name rails: VDD_3V3_DIG, VDD_3V3_ANA, VDD_1V1_CORE, VDD_1V8_DIG, VDD_1V8_ANA, etc.
-
Close all airwires on power pins and decouplers:
- Especially U5 buck in/out loops, U8 VCAP pins, U4 VCCPLL and VCCIO banks, ADC DVDD/AVDD and VREF decouplers.
-
Validate PMIC L/C selections and rail capacity:
- Confirm peak and average current per rail (MCU, FPGA, ADC digital, IOs).
- Confirm loop stability per DA9062 datasheet with your chosen inductors/caps.
-
Strengthen input protection:
- Add VBUS TVS, polyfuse, data-line ESD, and consider input LC.
-
Analog cleanliness:
- Keep VREF and ADC analog rails isolated via LC/RC filters, with star-ground at ADC.
- Ensure STM32 VDDA has its RC and local caps.
-
Decoupling completeness:
- Per device pin clusters, place 1× 0.1 uF per power pin (or per pair) plus 1–4.7 uF bulk per side of large ICs; place as close as possible to pins.
If you want, I can propose exact L/C values per DA9062 rail and a decoupling spreadsheet for each device pin cluster, and then wire the nets accordingly.
Calculate buck LC
Find input TVS
Rename power nets
Compute RC cutoff
Plot PDN impedance
To get started, talk to Flux or create a New Document.
![CT Scanner DAS Board [No Net Type] thumbnail](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzL0NULVNjYW5uZXItREFTLUJvYXJkLWltYWdlLXBuZy1iNWJkNTRhYi1hNGMyLTQ3ZTYtYjVkYi00NDA3ZjZmZjE4MDAucG5nIiwiZWRpdHMiOnsicmVzaXplIjp7IndpZHRoIjoxMzYsImhlaWdodCI6MTM2LCJmaXQiOiJjb250YWluIiwiYmFja2dyb3VuZCI6eyJyIjowLCJnIjowLCJiIjowLCJhbHBoYSI6MH19fSwib3V0cHV0Rm9ybWF0Ijoid2VicCJ9)