BoomPack Audio Project Overview
Started implementing a plan
#Goal
- Delete all existing PCB traces/routing geometry for the BoomPack Dual ESP32 Audio Pod while preserving schematic connectivity, component placements, board dimensions (75x75mm), and a 4-layer stackup and then reroute the board from scratch.
#Implementation plan
1. Inspect existing PCB layout
1. Identify and locate all stale routing objects including traces, vias, smart-vias, copper fills, floating copper, and dangling traces.
2. Confirm that schematic connectivity, component placement, board outline, and stackup are intact.
2. Remove stale routing objects
1. Batch delete all traces, vias, and copper elements that are flagged as stale or inactive.
2. Ensure that only essential elements (component pads, board outline, schematic nets) are retained.
3. Verify cleanup
1. Run a DRC inspection to confirm removal of all dangling traces, floating copper, and redundant routing objects.
2. Confirm that airwires remain as expected because the board is unrouted post-deletion.
4. Reconfigure and plan routing
1. Set up routing widths and parameters for differing signal types, including power/GND, UART/I2S, and control signals.
2. Use phase-based autorouting: route power and ground first, then critical signal pairs (UART/I2S), followed by remaining controls and headers.
5. Final verification
1. Re-run DRC to ensure there are no overlapping copper areas, stray airwires, or remaining stale objects.
2. Iterate cleanup actions until the board meets manufacturing criteria.
#Success criteria
- All stale routing objects are completely removed and the board is free from dangling traces and floating copper as verified by DRC.
- The board remains at 75x75mm with a 4-layer stackup and maintained component placements and schematic connectivity.
- All nets are outcome-routed based on defined routing priorities with a clear and manufacturable layout.
Task unable to complete.
3:27
Updated 3 layout rules
0:01
Set Smart Via's active to "false"
Set Smart Via's active to "false"
Set Smart Via's active to "false"
- Verified the board is still 75×75mm with a 4-layer stackup and component placements intact.
- Confirmed stale routing geometry remains: 476 trace segments, 39 smart vias, 92 vias, and 1 fill.
- Checked DRC status: airwire/dangling routing errors are still present, so the board is not yet clean or rerouted.
- ❌ Stale routing fully removed: not met.
- ✅ Board size/stackup/placement preserved: met.
- ❌ Board rerouted from scratch and manufacturable: not met.
- Board outline set to 75 mm × 75 mm rectangle with 3 mm corner radius.
- Stackup retained as 4-layer; both inner copper layers are configured as planes to support low-impedance power/ground distribution.
- Default signal trace width set to 0.25 mm.
- Preferred wider routing options set to 0.5 mm and 0.8 mm for 5V/GND/power paths.
- GND net biased to 0.8 mm preferred routing.
- Top edge: USB-C input, TP4056 charger, battery connector, power switch, boost converter, and 3.3V regulator grouped for short/high-current power paths.
- Center: RADIO and AUDIO ESP32-WROOM-32U modules placed close together for short crossed UART routing.
- Bottom edge: MAX98357A amplifier and speaker terminal placed together to keep speaker wiring and I2S routing clean.
- Left/right edges: programming headers and user switches placed for enclosure access.
- Board size: 75 mm × 75 mm.
- Copper layers: 4.
- Component aggregate occupied bounds after placement: approximately 73.18 mm × 71.69 mm, fitting inside the 75 mm board.
- Placement/routing density: nominal but workable.
- Remaining issue: routed traces have not been regenerated after the component move, so airwires remain and require a routing pass before fabrication.
- Route RADIO↔AUDIO UART first using short/direct traces.
- Route AUDIO→MAX98357A I2S lines next, keeping them direct and grouped.
- Route boost/5V/GND power paths with 0.5–0.8 mm widths where practical.
- Keep USB/charger/battery paths short and wide.
- Preserve clear antenna cable access at the ESP32-WROOM-32U U.FL ends.
Goal
Implemented layout strategy
Functional placement
Verification snapshot
Recommended routing priorities
