Project Specification
Version: 0.1.0
Date: ...
Author: ...
Status: ...
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1. Executive Summary
What board we're building and the intended outcome in one paragraph.
This project implements a complete synchronous buck converter around the TI TPS54336A family device (target MPN TPS54336ADRCR) to regulate a noisy 23 V to 25 V input (24 V nominal) down to a 5 V rail. The design must support 0.1 A to 2.0 A loads with operational load steps in 0.3 A increments up to 2.0 A while keeping output ripple within 5% of 5 V and mitigating input cable noise (1 m cable from remote PSU).
2. Goals and Non-Goals
What must be true in this rev, and what is explicitly out of scope.
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2.1 Goals
- Regulate 23 V to 25 V input to a stable 5 V output.
- Support load current range 0.1 A to 2.0 A (continuous).
- Handle load steps of 0.3 A up to 2.0 A without instability.
- Keep Vout ripple IC high-side FET -> SW node -> return to input cap).
- Keep SW node copper compact and away from feedback network.
- Route VSENSE divider to quiet ground; connect compensation components to IC ground reference.
- Place bootstrap capacitor close between BOOT and PH.
- Place input HF MLCCs close to VIN/GND pins.
5.4 Cost and Sourcing Constraints
Target cost range, availability requirements, preferred vendors/alternates policy.
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6. Assumptions and Dependencies
What we assume is true, and what the design depends on (parts, standards, external systems).
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7. Validation Criteria
What “done” means in terms of checks and evidence (not task lists).
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7.1 Acceptance Tests
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7.2 Review Checklist
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Appendix (Optional)
Any supporting urls, analysis, datasets, or taxonomy notes that informed this spec.
- Datasheet: TPS54336A (provided PDF in chat attachments)
- Datasheet references used for calculations:
- Inductor selection: Equation 19 with KIND guidance
- Output capacitor sizing: Equation 23 and transient criterion COUT > 2DeltaI/(fSWDeltaV)
- Output ripple ESR criterion: ESR < VOUT(ripple)/Iripple