Project File Analysis Request

flux

Work done
  • Audited the main schematic connectivity and confirmed the implemented signal path around U1, U2, IC1, U3, U4, U5, U6, Q1, FB1, J1, D1, D2, and L1.
  • Confirmed key nets are present and named: VBAT, V3P3, V3P3_A, V12, PIEZO_NODE, RX_IN, RX_STAGE1_OUT, RX_STAGE2_IN, RX_STAGE2_OUT, ENV_FILT, ADC_ENV, I2C_SCL, I2C_SDA, TMP117_ALERT, USB_5V, CC1, and CC2.
  • Identified unresolved schematic cleanup items: R19, R23, R24, C19, C22, and C23 still have floating terminals, and U5 still shows an unresolved local net (Net 1) plus R14 on Net 3.
  • Confirmed documented intentional exceptions: some spare GPIOs on U1 and USB data/SBU pins on J1 were intentionally left NC; the charge-status outputs on U2 and LED implementation were acknowledged but not finalized.
  • Renamed the project to ESP32-S3 Piezo TX RX Board.
  • Verified the board is configured as 2-layer, but current placement still violates the plan: the overall placed-component span is about 49.52 x 109.8 mm, well outside the required 50 x 50 mm envelope.
  • Verified manufacturability is not yet release-ready: no missing footprints were reported, but L1 remains a generic inductor and DRC still reports 97 airwires.
Success criteria review
  • ❌ Complete schematic with unintended opens resolved: not met. Several floating support parts remain and at least two anonymous local nets (Net 1, Net 3) still indicate unfinished RX/envelope wiring.
  • ❌ Design converged inside 50 x 50 mm with mixed-signal placement constraints: not met. Current placement height is about 109.8 mm.
  • ❌ ERC/DRC resolved or intentionally exempted and documented: not met. ERC warnings remain and DRC still shows 97 airwires.
  • ❌ Export-ready manufacturing package: not met, because the layout is not yet placement/routing complete.
Next steps I reached the limit of what I can finish autonomously here. The remaining work depends on PCB placement and routing operations I cannot perform directly in-chat. After the layout is compacted into 50 x 50 mm and the airwires are routed, I can continue with final schematic cleanup, update Design Notes, re-check ERC/DRC, and prepare manufacturing exports.
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Schematic

Layout

Preview

U1
Design Notes
System Summary
Compact 2-layer ESP32-S3 piezo TX/RX board targeting a 40 mm to 60 mm PCB. The design uses a shared piezo node for 3 MHz transmit and receive, LiPo charging from USB 5 V, 3.3 V regulation with separated analog rail, a boosted transmit rail near 12 V, and a protected 2-stage analog receive chain.
Architecture Decisions
  • Main controller: ESP32-S3-MINI-1 module.
  • Charger: TP4056 from USB 5 V to single-cell LiPo.
  • Main 3.3 V rail: TLV75533.
  • Analog 3.3 V rail: ferrite bead isolated from 3V3_MAIN.
  • TX rail: boost converter to approximately 12 V with pulsed-load support.
  • TX driver: low gate charge NMOS low-side pulser with gate resistor and pulldown.
  • Shared transducer node: PIEZO_NODE.
  • RX input protection: series resistor, Schottky clamps to 3V3_ANALOG and AGND, small shunt capacitor.
  • RX front end: two OPA836 stages with mid-supply bias around 1.65 V, envelope detection, low-pass filter, and ADC feed.
  • Sensor: TMP117 on I2C with 4.7k pull-ups.
  • Grounding: AGND and DGND partitioned with single star connection near RX front end.
Initial Layout Intent
  • Piezo/transducer connector centered.
  • OPA836 receive chain within 10 mm of PIEZO_NODE.
  • Boost converter and TX switching loop far from RX front end.
  • ESP32 and digital support parts grouped in digital region.
  • Decoupling capacitor placed at each IC supply pin.
Implemented Schematic Blocks
  • ESP32-S3-MINI-1 main controller added as the digital core.
  • USB-C 5 V input added with dual 5.1k CC resistors for sink configuration.
  • TP4056 charger connected to the USB input and battery rail.
  • TLV75533 low-noise 3.3 V regulator added with a ferrite-bead isolated analog rail.
  • MP3437 boost converter stage added for the approximately 12 V transmit rail.
  • AO3400A NMOS, gate resistor, and pulldown added for TX pulsing.
  • Shared PIEZO_NODE, Schottky clamps, series RX resistor, and small shunt capacitor added.
  • Two OPA836 receive stages, mid-supply bias network, envelope detector, and ADC interface added.
  • TMP117 sensor connected to the ESP32 I2C bus with 4.7k pull-ups.
Current Review Status
  • Layout canvas is set to 50 mm x 50 mm, 2-layer.
  • The schematic still needs cleanup for several intentionally unused or not-yet-tied pins, especially spare ESP32 GPIOs, USB data pins, TP4056 status pins, and a few RX/LED support parts.
  • PCB placement is still in the default spread-out state and must be re-arranged to satisfy the mixed-signal partitioning constraints.

  • System Summary

  • Architecture Decisions

  • Initial Layout Intent

  • Implemented Schematic Blocks

  • Current Review Status