Update Pad Specifications and Route Traces
Thought for 4 sec
I’ll update the VIN and V− pads to through-hole footprints, then inspect and route the remaining airwires and verify the result.
Worked for 41 sec
I found J1 pin 1 is VIN and J2 pin 1 is V−/VNEG; I’m applying explicit through-hole pad rules to those two pads, then I’ll rerun routing.
Worked for 1 min 17 sec
The two power pads now have explicit through-hole settings. The router check flagged congestion, so I’m going to spread the crowded center components slightly before routing.
Worked for 5 mins 17 sec
Done: J1 Pin 1 (VIN) and J2 Pin 1 (V−/VNEG) are now explicit through-hole pads, and auto-routing completed successfully with 94 routing nodes added.
Open items:
- Airwire check now reports no open/error/warning airwires.
Suggested next steps:
- Run a full DRC/ERC pass.
- Review routed trace paths around U1 and the trimmers.
- Export manufacturing files when ready.
Run checks and export
Run full DRC/ERC
Review critical routing
Check manufacturability
Export fab files
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Project Specification — Compact AD620 IA Module
Project Overview
Draft compact instrumentation amplifier module based on the AD620 SOIC-8. It provides socketed input/output connections, adjustable gain, and adjustable zero/reference offset using two trimmer potentiometers.
Intended Use
Small prototype analog front-end module for amplifying low-level differential signals. Intended as a compact/thin PCB similar to the provided reference image.
What the Device Should Do
- Accept VIN, GND, SIGNAL+, and SIGNAL- on an input socket.
- Provide V-, GND, VOUT, and GND on an output socket.
- Amplify the differential input using AD620.
- Allow user adjustment of gain with a potentiometer.
- Allow user adjustment of output reference/zero with a potentiometer.
System Architecture
Input socket → input EMI/series network → AD620 instrumentation amplifier → VOUT socket. VIN and V- power the AD620; REF is driven by the zero/reference trimmer.
Hardware Subsystems
- Amplifier: AD620BRZ SOIC-8.
- Gain adjust: 100kΩ SMD trimmer plus 100Ω series limiter between RG pins.
- Reference adjust: 100kΩ SMD trimmer between VIN and V-; wiper feeds REF through 1kΩ.
- Power bypass: 100nF capacitors from VIN to GND and V- to GND.
- Input filter: 100Ω series resistors and 100pF differential capacitor.
- Connectors: two 1x4 2.54mm female socket headers.
Interfaces and Connections
Table
| Connector | Pin | Function |
|---|---|---|
| J1 | 1 | VIN / AD620 +VS |
| J1 | 2 | GND |
| J1 | 3 | SIGNAL+ |
| J1 | 4 | SIGNAL- |
| J2 | 1 | V- / AD620 -VS |
| J2 | 2 | GND |
| J2 | 3 | VOUT |
| J2 | 4 | GND |
Power and Runtime Expectations
AD620 supports ±2.3V to ±18V supplies per datasheet. User must supply VIN and V- rails appropriate for the desired input/output swing.
Physical Design Expectations
Target is very small and thin. Selected SOIC-8 AD620, 0402 passives, SMD top-adjust trimmers, and socket headers. Final board layout should place headers on opposite edges and trimmers on the right side like the reference image.
Important Design Decisions
- Used SMD 100kΩ trimmers because no 10kΩ SMD top-adjust trimmer was available in the Flux library; this preserves the thin-module goal.
- Added 100Ω in series with the gain trimmer to limit maximum gain to approximately 495.
- REF trimmer spans VIN to V-; avoid setting REF too close to rails because the AD620 datasheet notes REF should stay within about 2V of the supply rails.
Assumptions
- VIN is the positive supply rail, not a signal input.
- V- is provided externally on J2 pin 1.
- GND is the signal/reference ground shared by both sockets.
- The user wants socket headers rather than solder pads only.
Change Notes
Initial schematic created with main IC, two trimmers, four passives, and two socket headers.
Project Overview
Intended Use
What the Device Should Do
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
