graph LR A[PLCC-52 Interposer<br/>(Paula)] -->|Original Signal Path| B[Paula Footprint] C[28-pin SID Socket] -->|Pin-Compatible Signals| B D[Clockport Interface] -->|Decode/Control| E[74HCT Buffer] E --> C subgraph Oscillators F[PAL Oscillator] G[NTSC Oscillator] H[Slide Switch] F --> H --> C G --> H end I[(+12 V Rail from MB)] --> J[Filtering/Decoupling] J --> C K[(+5 V Rail from MB)] --> L[Decoupling] L --> C C -->|Audio Out| M[Op-Amp Mixer] M --> N[Volume Pot] N --> O[RCA Audio Out] subgraph Grounding P[GND Star Point] B & C & E & J & L & M --> P end

Standard 4-layer stackup: Top signal copper, Inner1 GND plane, Inner2 VCC plane, Bottom signal copper

U2 (7.62 mm × 35.56 mm), U3 (19.2 mm × 19.2 mm), U1 (8.6 mm × 3.9 mm), Y2 (11.4 mm × 4.7 mm), Y1 (3.2 mm × 2.5 mm), SW1 (8.5 mm × 3.0 mm), Cx/Rx (1.6 mm × 0.8 mm)

U2 (DIP762W60P254L3556H510Q28, 7.62 mm x 35.56 mm), U3 (PLCC-52_L19.2-W19.2-P1.27-LS21.0-L, 19.2 mm x 19.2 mm), U1 (SOIC-14_L8.6-W3.9-P1.27-LS6.0-BL, 8.6 mm x 3.9 mm), Y2 (CRYSTAL-SMD_L11.4-W4.7-LS12.7, 11.4 mm x 4.7 mm), Y1 (OSC-SMD_4P-L3.2-W2.5-BL, 3.2 mm x 2.5 mm), SW1 (JS102011JCQN, 8.5 mm x 3 mm), C3/C4/C2/C5/C6 (CAPC1608X90, 1.6 mm x 0.8 mm), C1/C8/C9/C10/C11/C7 (SMD_0603_1608Metric, 1.6 mm x 0.8 mm), R1/R2 (SMD_0603_1608Metric, 1.6 mm x 0.8 mm)

10 kΩ