2

GND. Connect to solid ground reference. Keep return for input/output capacitors local; avoid sharing with noisy digital currents.

Texas Instruments

Regulator

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OUT (regulated 5 V output). Route to NP5V net. Place output bypass capacitor(s) close between OUT (Pin 1) and GND (Pin 2).

LP2950-50LPRE3 (TO-92-3, viewed from flat face, leads downward): Pin 1 = OUT (regulated 5 V output), Pin 2 = GND, Pin 3 = IN (unregulated input). Do NOT assume 78L05 pinout; 78L05 in TO-92 is typically 1 = IN, 2 = GND, 3 = OUT, which is reversed relative to LP2950-50.

R8

Power Conversion

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5 V low-dropout linear regulator for pedal power rail NP5V. TO-92-3 pinout (flat face, leads downward): Pin 1 = OUT (regulated 5 V), Pin 2 = GND, Pin 3 = IN (unregulated VIN). Do NOT use 78L05 pin mapping.

flowchart TD P(Power) --> IB(Input Buffer) IB --> DE(Delay Engine) DE --> F(Filters) F --> OB(Output Buffer) OB --> OUT(Output) F --> FB(Feedback) FB --> DE IB --> TB(True-Bypass) TB --> OUT

VCO

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Power

Place input and output bypass capacitors as close as possible to LP2950-50 pins: (1) Input capacitor (e.g., 1–10 uF electrolytic or tantalum plus 100 nF ceramic) from IN (Pin 3) to GND (Pin 2), (2) Output capacitor (e.g., 1–10 uF low-ESR electrolytic or tantalum plus 100 nF ceramic) from OUT (Pin 1) to GND (Pin 2). Keep these loops compact, use a solid ground reference, and avoid routing noisy digital currents through the regulator ground return.

R7

LP2950-50LPRE3

92-TO

Battery

IN (unregulated VIN from DC jack PWR1 center pin). Place input bypass capacitor(s) close between IN (Pin 3) and GND (Pin 2).

Consumer Electronics

Linear Regulator

DD