Guitar Pedal Schematic Request

Updated properties for 1 object

0:16

Set R10's Part Type to "Fixed Resistor"

Set R10's Resistor Type to "Chip SMD"

Set R10's Package or Case Code to "R_0603_1608Metric"

Set R10's Manufacturer Part Number to "GENERIC-RES-0603"

Set R10's Mount to "Surface Mount"

90 days

Added LP2950-50 pinout guidance

1:55

Started: Add a project property containing the LP2950-50 pinout note and recommended capacitor placement guidance.

90 days

Updated 14 document properties

0:20

Set Part Type to "Linear Regulator"

Set Manufacturer Part Number to "LP2950-50LPRE3"

Set Manufacturer Name to "Texas Instruments"

Set Package or Case Code to "92-TO"

Set Logic Function to "Regulator"

Set Role to "Power Conversion"

Set Role Details to "5 V low-dropout linear regulator for pedal power rail NP5V. TO-92-3 pinout (flat face, leads downward): Pin 1 = OUT (regulate..."

Set DD3 Pin 1 Function to "OUT (regulated 5 V output). Route to NP5V net. Place output bypass capacitor(s) close between OUT (Pin 1) and GND (Pin 2)."

Set DD3 Pin 2 Function to "GND. Connect to solid ground reference. Keep return for input/output capacitors local; avoid sharing with noisy digital curre..."

Set DD3 Pin 3 Function to "IN (unregulated VIN from DC jack PWR1 center pin). Place input bypass capacitor(s) close between IN (Pin 3) and GND (Pin 2)."

Set LP2950-50 Pin Note to "LP2950-50LPRE3 (TO-92-3, viewed from flat face, leads downward): Pin 1 = OUT (regulated 5 V output), Pin 2 = GND, Pin 3 = IN ..."

Set LP2950-50 Layout Guidelines to "Place input and output bypass capacitors as close as possible to LP2950-50 pins: (1) Input capacitor (e.g., 1–10 uF electroly..."

Set Max Output Voltage to "5"

Set Net Type to "Power"

90 days

Worked

0:29

90 days

flux

0:00

Work completed
  • Project description and system architecture fully updated
  • All core ICs (PT2399 delay, TL072 buffers, LP2950-50 regulator) placed and configured
  • All passive components added and wired per PDF schematic
  • 3PDT true-bypass switch with LED indicator implemented
  • Off-board pads for three 50 kΩ B potentiometers and two 1/4″ mono jacks (plus DC barrel jack) added
  • Component properties annotated and ERC errors resolved
Success criteria
  • ✅ Schematic accurately mirrors the provided PDF
  • ✅ 3PDT true-bypass circuit with LED indicator implemented
  • ✅ LP2950-50 correctly integrated and annotated with pinout guidance
  • ✅ Off-board pads for all pots and jacks added with correct labels
  • ✅ Passed ERC with no outstanding errors
Next step Proceed to PCB layout: review and assign footprints, configure stackup, place components, and route all nets.
90 days
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Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

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    Digital Delay Pedal S.O. (Solo)

    Digital Delay Pedal S.O. (Solo) thumbnail
    MODDED Boy in Well Digital Delay Pedal (PT2399-Based Guitar Effect) w/ Self Oscillation Switch

    Properties

    2

    GND. Connect to solid ground reference. Keep return for input/output capacitors local; avoid sharing with noisy digital currents.

    Texas Instruments

    Regulator

    {}

    OUT (regulated 5 V output). Route to NP5V net. Place output bypass capacitor(s) close between OUT (Pin 1) and GND (Pin 2).

    LP2950-50LPRE3 (TO-92-3, viewed from flat face, leads downward): Pin 1 = OUT (regulated 5 V output), Pin 2 = GND, Pin 3 = IN (unregulated input). Do NOT assume 78L05 pinout; 78L05 in TO-92 is typically 1 = IN, 2 = GND, 3 = OUT, which is reversed relative to LP2950-50.

    5

    V

    solderpad.org/licenses/SHL-2.1/

    R8

    9

    V

    Power Conversion

    {}

    5 V low-dropout linear regulator for pedal power rail NP5V. TO-92-3 pinout (flat face, leads downward): Pin 1 = OUT (regulated 5 V), Pin 2 = GND, Pin 3 = IN (unregulated VIN). Do NOT use 78L05 pin mapping.

    flowchart TD P(Power) --> IB(Input Buffer) IB --> DE(Delay Engine) DE --> F(Filters) F --> OB(Output Buffer) OB --> OUT(Output) F --> FB(Feedback) FB --> DE IB --> TB(True-Bypass) TB --> OUT

    VCO

    {}

    {}

    Power

    Place input and output bypass capacitors as close as possible to LP2950-50 pins: (1) Input capacitor (e.g., 1–10 uF electrolytic or tantalum plus 100 nF ceramic) from IN (Pin 3) to GND (Pin 2), (2) Output capacitor (e.g., 1–10 uF low-ESR electrolytic or tantalum plus 100 nF ceramic) from OUT (Pin 1) to GND (Pin 2). Keep these loops compact, use a solid ground reference, and avoid routing noisy digital currents through the regulator ground return.

    R7

    LP2950-50LPRE3

    92-TO

    Battery

    IN (unregulated VIN from DC jack PWR1 center pin). Place input bypass capacitor(s) close between IN (Pin 3) and GND (Pin 2).

    Consumer Electronics

    Linear Regulator

    DD

    Pricing & Availability

    Distributor

    Qty 1

    Arrow

    $2.37–$3.00

    Digi-Key

    $8.04–$9.53

    LCSC

    $9.27–$9.53

    Mouser

    $8.87

    TME

    $0.61

    Verical

    $2.59–$3.05

    Controls