Project Error Review

Power-pin net mapping (as currently wired)

Table


ICPinPin #Net it’s onNotes
U2VIN3^+12VNet currently only shows U2:VIN connected.
U2GND1^CHASSISThis is why ERC reports a single-pin net for ^CHASSIS.
U3AVDD4^+3V3Only pin 4 is connected to ^+3V3 right now. Other AVDD pins are not on this net.
U3AVDD8(unconnected)Not on any net.
U3AVDD11(unconnected)Not on any net.
U3AVDD15(unconnected)Not on any net.
U3AVDD17(unconnected)Not on any net.
U3AVDD21(unconnected)Not on any net.
U3VDD28(unconnected)Not on any net.
U3GND29(unconnected)Not on any net.
If you want, I can also list the AGND pins for U3 (there are several) and what nets they’re currently on, since those are part of the power/return path.
List U3 AGND nets
Check missing decoupling
Inspect U2 output net
Find U3 power pins
Fix CHASSIS usage

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    Continuous Brown Massive Robot Spider thumbnail
    ESP32-S3-WROOM 12V Relay Controller: 8x Opto-Isolated 127/220VAC Inputs, 8x 10A NO/COM Relays, Wi-Fi/BLE/Ethernet, I2C/SPI

    Properties

    Diagram


    ""High Voltage AC Domain"" ""Low Voltage Domain"" "IN1..IN8 node_2p terminals" "Fuse per channel" "MOV per channel" "Bridge rectifier per channel" "Current limit resistor" "Optocoupler per channel" "12V DC Input" "12V -> 3.3V regulator" "ESP32-S3-WROOM" "SPI Ethernet controller + MagJack" "GPIO expander (optional)" "Relay drivers + flyback" "Relays x8 node_10A" "OUT1..OUT8 NO+COM terminals" "I2C and SPI headers"

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    Controls