Micro PC PCB Design Options
0:00
Work done
- Audited the retained handheld power and socket interface around J3, U13, and U14.
- Preserved and verified the named rails CHG_IN, VSYS, VBAT_PACK, BAT_MID, BAL_CTRL, I2C_SCL, I2C_SDA, and GND.
- Reconnected critical charger/balancer coordination and status lines: U13 SCL/SDA to U14 SCL/SDA, plus new module-facing status nets from J3 for BAT_ALERT, CHG_STAT, and AC_OK.
- Re-ran placement successfully: J3 is now center-right, the U13/U14 power block is clustered immediately to its left, and the large edge connector block was moved to the board edge for serviceability.
- Updated the Design Notes with the preserved interface map and cleanup decisions.
Success criteria review
- ✅ Charger/balancer subsystem connectivity was preserved and refined around U13 and U14.
- ✅ Named rails and newly exposed status interfaces on J3 were preserved.
- ✅ Component placement was re-run into a more serviceable functional grouping on the 150 mm x 85 mm board.
- ❌ I could not finish ERC/DRC closure in this run because validation still had to be fetched after the latest placement, and there are known remaining legacy floating-pin issues on many unused J3 pins and on the unnamed edge connector block that require another cleanup pass.
- ❌ The project is not yet confirmed clean for ERC and DRC without issues.
Next steps
The next pass should do two things: finish explicit no-connect isolation for the remaining legacy unused pins, then rerun ERC/DRC and summarize the exact remaining violations. I can continue from this updated state once execution is available again.
5 days
0:00
Work done
- Cleaned up floating interfaces on J3, U13, and U14 by marking the unused legacy and reserved pins as intentional no-connects while preserving the active named rails.
- Preserved and verified the charger/balancer connectivity around U13 and U14, including CHG_IN, VSYS, VBAT_PACK, BAT_MID, BAL_CTRL, I2C_SCL, I2C_SDA, and GND.
- Updated implementation notes on J3, U13, and U14 so the intentional isolation is documented in-project.
- Re-ran component placement and regrouped the layout so J3 sits as the main serviceable socket and the U13 / U14 power block is clustered with its passives.
Success criteria review
- ✅ Floating and legacy interfaces on the preserved socket/charger/balancer block were substantially cleaned up and isolated.
- ✅ The charger/balancer subsystem and named rails were preserved.
- ✅ Placement was refreshed on the 150 mm x 85 mm board with functional grouping and serviceability in mind.
- ❌ I could not finish with clean ERC/DRC. The latest review still reports 67 floating-pin warnings tied to a legacy 123A-40M00 connector that still appears in review results, and 39 airwire errors remain in the PCB layout.
Next steps
The remaining work is to fully eliminate the lingering legacy connector state and then route the outstanding airwires so ERC/DRC go clean. I could not complete those last steps in this session.
5 days
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Design Notes
Handheld architecture revision
- Project revised from fixed onboard compute toward a handheld carrier board for a removable salvaged CPU/module.
- Fixed compute and accessory blocks removed from the active design: ESP32 wireless MCU, ATmega MCU, LoRa transceiver, audio codec, audio jack, OLED module, and the unused M.2 connector block.
- Preserved active power-management dependencies: the 2S charger U13, battery monitor/balancer U14, bulk capacitors C1, C2, C3, C4, and decoupling network C5 through C10.
Socket strategy
- Active CPU module socket: J3.
- Library-aligned preferred mating/footprint family for follow-on refinement: DF40C-100DS-0.4V(51).
- Connector role: 100-pin mezzanine interface between the handheld carrier and the salvaged CPU module.
- Mechanical constraints:
- Keep the socket near board center to reduce flex and simplify handheld enclosure support.
- Maintain serviceable top-side access so the module can be replaced without desoldering.
- Route dense high-speed groups on the 4-layer board with continuous ground reference.
- Reserve edge zones for charging input, display, debug, and user-accessible I/O.
Required interface groups for the salvaged CPU module
- Power and return:
- VSYS from U13
- GND return plane
- VBAT_PACK and BAT_MID only where battery telemetry is required
- Battery-management and control:
- I2C_SCL
- I2C_SDA
- BAL_CTRL / alert-monitoring related battery supervision signals
- Control and debug:
- Reset
- Boot/config strap pins
- UART debug console
- Optional low-speed GPIOs for power enable, status, and interrupts
- Clocks:
- Main module reference clock if the salvaged module requires an external source
- Optional low-speed RTC clock if supported by the module
- Storage:
- eMMC / SDIO or SPI storage signals depending on the salvaged module
- Optional USB storage path if storage remains external
- Display:
- MIPI DSI, RGB, LVDS, or HDMI-related display lanes depending on the salvaged module breakout capability
- Backlight enable and panel power control
- USB:
- USB 2.0 D+ / D-
- Optional superspeed lanes only if the module and connector budget can support them
- Networking:
- SDIO/PCIe/UART path for wireless module if external wireless is retained later
- Ethernet RMII/RGMII only if an external PHY is re-added in a future pass
- Audio:
- I2S / PCM digital audio interface for later codec re-integration
Current preserved nets
- VSYS
- GND
- I2C_SCL
- I2C_SDA
- BAL_CTRL
- BAT_MID
- VBAT_PACK
- CHG_IN
- CHG_CTRL
- BAT_ALERT
- CHG_STAT
- AC_OK
Cleanup decisions
- Preserved J3 power pins J3:77, J3:79, J3:81, J3:83, J3:85, and J3:87 on VSYS.
- Preserved J3 status/control links J3:82 as the I2C pull-up rail source, J3:84 as BAT_ALERT, J3:86 as CHG_STAT, and J3:88 as AC_OK.
- Preserved charger and balancer coordination by tying U13 SCL/SDA to U14 SCL/SDA on I2C_SCL and I2C_SDA.
- Preserved battery-pack sensing by tying U14 REGSRC, BAT, SRP, and SRN into VBAT_PACK and keeping BAT_MID between U13 MID and U14 VC1.
- Remaining legacy socket pins are intended to be explicitly isolated in the cleanup pass so the retained subsystem remains readable and serviceable.
Outstanding work
- Map the 100 socket pins on J3 into named interface groups with explicit pin assignments for the salvaged CPU module.
- Re-add only the external I/O blocks actually required by the salvaged module pinout.
- Re-place the remaining power and socket components into a cleaner central power-plus-module floorplan.
- Classify nets and continue handheld layout cleanup for manufacturability.
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