Product Development Lab Report Review

flux

Got it. I’ll treat the output connector side as part of the mains-side zone too.
Updated connector clearance rule
Keep an 8 mm preferred clearance around each output connector:
That means:
  • 8 mm preferred from output connector copper/pads to any logic traces or logic components
  • 6 mm absolute minimum if the board gets tight
  • no SPI, I2C, ESP32 GPIO fanout, EN/BOOT, or display routing through that connector/output corridor
This fits the layout workflow where placement constraints and grouping should be defined before broader placement/routing
Updated mains-side boundary
Treat this whole area as one protected zone:
  • relay contact sides of K1, K2, K3, K4
  • output connectors U5 to U8
  • the short copper paths between each relay contact and its connector
Practical floorplan rule
  • Logic/UI zone: U1, U2, LCD1, U4, buttons, logic passives
  • Power zone: U3, input connector, input caps
  • Relay coil/driver zone: Q1 to Q4, D8 to D11
  • Mains/output zone: relay contact sides plus U5 to U8, all with 8 mm preferred clearance to logic
Updated spacing table

Table

AreaPreferred clearanceMinimum
Relay contact side to logic8 mm6 mm
Output connector side to logic8 mm6 mm
Relay/output copper corridor to logic traces8 mm6 mm
Adjacent uncertain-load output nets6 mm3 mm
If you want, I can next turn this into a single consolidated keepout spec for U1, U2, LCD1, K1 to K4, and U5 to U8.
Consolidate keepout spec
Add creepage slots
Placement order
Check layout risks

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