The piezo is primarily capacitive, so current is set by slew rate:

For a sine-wave output:

Confirmed revised requirement: the maximum output is 400 V peak, single-ended output, gain is 40 from a 10 V maximum input, and the 3 A threshold means peak output/load current.

Under that assumption:

For the revised design target, the output stage is sized by peak reactive current rather than real power alone. With 400 V peak into 2.5 nF, the 3 A peak current limit is reached at about 477 kHz. At that point Vrms is about 283 V and Irms is about 2.12 A, so the output network, MOSFETs, current sense path, connector, and magnetic/filter parts must tolerate roughly 600 VA of circulating reactive power even though the real power delivered to an ideal capacitor is near zero. At 500 kHz the controller must reduce amplitude to about 382 V peak to keep the current at 3 A peak.

Power-path design rule for schematic capture:

Therefore the revised requirement set "400 V peak, 2.5 nF, 0-500 kHz, 3 A peak current limit" is nearly feasible but still slightly exceeds the current limit at the top frequency for a full-amplitude sine wave. The recommended design rule is to allow 400 V peak up to about 477 kHz, then limit amplitude to about 382 V peak at 500 kHz, unless the 3 A limit has intentional comparator tolerance/headroom.

Important: ideal capacitive load real power is low, but the amplifier, transformer or matching network, switches, current sense, snubbers, and protection circuits must withstand the circulating reactive current.

Preferred architecture for this requirement:

A linear high-voltage amplifier is not the preferred first choice unless the operating frequency, duty cycle, and distortion requirements are modest. At high frequency, a linear stage driving a capacitive piezo can dissipate hundreds of watts even when the piezo consumes little real power.

220 VAC rectifies to approximately:

This has major implications:

Minimum required protection and safety functions:

China-preferred sourcing is realistic for a discrete full-bridge/resonant architecture. Candidate supplier categories to evaluate during detailed design:

Exact parts must be selected only after datasheet review for voltage, current, SOA, switching loss, gate charge, isolation rating, creepage/clearance, and thermal limits.

The following items are now confirmed:

The next step still requires these answers:

Before schematic capture, keep the revised protection rule explicit: implement frequency-dependent amplitude limiting so the output can reach 400 V peak up to about 477 kHz into 2.5 nF, and rolls off to about 382 V peak at 500 kHz if the 3 A peak limit is fixed. If full 400 V peak at 500 kHz is mandatory, the peak current limit must be at least about 3.14 A plus margin.

Initial schematic capture has started. The following parts have been added to the schematic but are not yet fully wired:

Important stop condition discovered during schematic capture:

Open architecture decision before safe completion:

Until one of these is selected, the already-added schematic components should be treated as a partial capture, not a safe manufacturable design.

The user approved the internal-isolation approach while keeping only three external interfaces: 220 VAC power input, low-voltage signal input, and high-voltage signal output. The schematic has now been extended from partial capture to a functionally wired first-pass architecture.

Implemented blocks:

Validation result:

Important remaining engineering risks before layout or fabrication:

Next recommended step:

Run circuit-level simulation of the PWM modulator, half-bridge, current limit, and piezo/output network before moving to PCB layout. Only after the waveform, current limit, switching loss, and thermal behavior are acceptable should the design proceed to board sizing and component placement.