PCB Design for Sawtooth VCO
Thought for 9 sec
Work done
- Built the core schematic around Q1, Q2, Q3, Q4, Q5, and U1, with Eurorack power input on J1 and jack I/O on J2, J3, and J4
- Assigned 1% metal-film values to R1 through R13, set C1 as the NP0/C0G timing capacitor, and added the required 10 uF plus 100 nF rail decoupling with C2, C3, C4, and C5
- Configured the PCB to 100 mm x 50 mm with a Standard 2 Layer stackup, documented the architecture in the Project Specification, and exported manufacturing data: https://cdn2.flux.ai/flux-comment-files/files/commentFileId-30c93f4c7c553eb977ae50922cf4544cf1898b984ec3eac2f095eeba2804a818.csv?GoogleAccessId=autopilot-sa-d60c62b%40graviton-mvp.iam.gserviceaccount.com&Expires=4929850091&Signature=v5EmHfh1cTToYGkNeEO9l1S%2Fkp7zny3c2jdGnPDNo7Fi0OC80H3KI4%2FZDDZxvdBcLUlvTS7DdLmUhONZKkkzXDpMu0Citt%2Fbp8gsguK7cvuSRH4zJtGmwEi7vm21iHon4zT%2Fc%2F7Hx9aqpWSNNfnMGA%2Fo9iPZY0E6cjTtd29LzKWlFRe6nwBWfxmC9KhhCzcjHksPxmlOhBC6sgAXkf23qSU19oS2JgkpSuUsFgeuH6tF73VVba3xHgRX778cj60lBfEh3ONiIrJVm19cJEqtDkK5VH50MY8M95yueFOJQXQgsHAJ7JRLtCh6B%2Bnmgq9bj2VqRJqv1O23aI8%2Fr0Mn5Q%3D%3D and eurorack-sawtooth-core-vco.d356
Success criteria review
- ✅ Required active devices, precision resistors, NP0 timing capacitor, and rail decoupling are present in the design
- ✅ Layout size is set to 100 mm x 50 mm and the board stackup is now 2-layer
- ✅ BOM and netlist exports were generated
- ❌ The 4 mounting holes were added in the schematic but have not yet been position-verified in the PCB
- ❌ The detailed 2-layer routing plan is only partially implemented: the critical guidance is to keep the C1 / Q1 / Q2 high-impedance summing region compact, place U1 and the square-output path away from that node, route saw and square outputs separately, and use the bottom layer as a continuous ground reference, but actual placement optimization and routing verification still remain
Next steps
Finish PCB placement by positioning the four mounting holes and analog core, then run airwire review and finalize the low-bleed routing strategy. I can continue with that next.
Create the VCO schematic
Set board constraints
Add required passives
Prioritize quiet layout
Generate BOM and reviews
Refine this doc
Ask about this doc
Project Specification
Scope
Design and implement a professional Eurorack sawtooth-core VCO using a discrete transistor exponential converter and reset circuitry, operating from plus and minus 12 volt rails.
Architecture
Diagram
Requirements
- Use 2N3904 and 2N3906 transistors in the exponential converter and reset circuitry.
- Use a TL072 op amp section as the square-wave comparator and produce a 0 V to 5 V square-wave output.
- Use 1 percent metal film resistors throughout the analog core.
- Use a C0G or NP0 timing capacitor in the saw-core integrator.
- Include 10 uF electrolytic and 100 nF ceramic decoupling on each supply rail.
- Fit the PCB layout into a 100 mm x 50 mm board outline.
- Use a 2 layer PCB with a solid ground plane on the bottom layer.
- Keep the high impedance summing node short and physically isolated from the square-wave path to minimize bleed.
Implementation Notes
- Prefer through-hole transistor and op amp packages for classic analog serviceability and easy thermal pairing where available.
- Thermally couple the matched 2N3904 pair used in the exponential converter placement.
- Keep comparator output routing away from the timing capacitor and summing node.
Design Summary
Status: Draft / Review / Approved
Manufacturing target: Prototype / EVT / DVT / PVT / Production
Software / firmware: repository link
Scope
Purpose
In scope
Out of scope
System context
Requirements
Functional
Electrical
Mechanical / environmental
Key constraints
Dependencies and risks
Dependencies
Key risks
Validation
Success criteria
Planned checks
Release-facing notes
Expected deliverables
Special release notes
Change notes / open questions
Changes in this revision
Open questions
Scope
Architecture
Requirements
Implementation Notes
Design Summary
Scope
System context
Requirements
Functional
Electrical
Mechanical / environmental
Key constraints
Dependencies and risks
Validation
Release-facing notes
Change notes / open questions
