# Project Specification ## Project Overview **Status:** Approved architecture; Stage-1 schematic in progress. Two mechanically distinct, all-in-one ESP32-S3 rotary UI controller PCBs share one logical compute/UI/USB/expansion core. Variant A adds isolated IEEE 802.3af PoE and 100BASE-T Ethernet. Variant B adds protected 1-cell LiPo charging, power path, and low-IQ buck-boost power. No daughterboard and no display in v1. ## Intended Use Production-intent prototypes for a wall-box PoE controller and a screw-serviceable battery/Wi-Fi controller. **Duty models differ by variant**: the PoE variant is **always-on** (never sleeps — continuous network presence, like the fielded v1 units); the battery variant deep-sleeps, with local rotary interaction waking the ESP32 and scheduled network checks/OTA windows. ## What the Device Should Do - Read a mechanical rotary encoder and integrated push switch, including deep-sleep wake (battery variant; the PoE variant is always-on and needs no wake path, though the wake-capable GPIO choice is shared core design and costs nothing). - Indicate state with one addressable RGB LED that defaults off. - Program/debug over native USB-C and support robust dual-slot OTA in 16 MB flash. - Expose internal future-display I2C, SPI, power, and spare GPIO signals. - PoE variant: operate from standards-compliant isolated PoE and communicate by 100BASE-T. - Battery variant: operate for at least one week, charge from magnetic 5 V or USB-C, and prevent source backfeed. ## Main Features - ESP32-S3-WROOM-1-N16R8 module: PCB antenna, 16 MB flash, 8 MB PSRAM. - Native USB 2.0 device data, ESD protection, independent 5.1 kΩ CC pulldowns, BOOT and RESET. - Encoder: **Bourns PEC11R-4220F-S0024** (selected) — 24 detents / 24 pulses per revolution (1:1, one full quadrature cycle per detent), momentary push switch, 20 mm flatted (D-flat) metal shaft. Satisfies the resolution-critical rule: PEC11R ships in pulse/detent combinations where pulse count ≠ detent count (e.g. 12 pulses with 24 detents), which would reproduce v1's every-other-detent behavior in hardware, unfixable in firmware — this variant's 24/24 avoids that. Note "-ND" seen on DigiKey is their catalog suffix, not part of the Bourns part number. Residual check before quantity order: confirm 20 mm shaft length against final plate thickness + knob stack-up (15/25/30 mm variants exist). - ESD protection on encoder A/B/switch lines (TVS array). Included by decision: the metal shaft/bushing is the primary user touchpoint, a plastic plate provides no discharge path to ground, so user ESD arrives on the signal lines; a single small TVS array is negligible cost/complexity. Bond the encoder's metal bushing/mounting nut to logic GND (SELV throughout, no isolation conflict on the shared core). - WS2812B-2020 RGB LED with local bypass and data default-low bias. - 2×5 internal display expansion connector; one I2C pull-up pair and default-high SPI chip select. - Variant-only power rails and connectors are explicitly named. ## System Architecture ```text Shared logical core (instantiated on each all-in-one PCB) USB-C -> protection -> ESP32-S3 <- encoder / RGB / expansion | +--------------+--------------+ | | PoE/Ethernet PCB Battery/Wi-Fi PCB RJ45+magnetics -> PoE PD -> 5V Mag 5V --|>|--+ RJ45 PHY pairs <-> W5500 USB 5V --|>|--+-> charger/power path LiPo -> buck-boost -> 3V3 ``` ## Hardware Subsystems ### Shared core/UI/USB Separate ESP32-S3 module instance per physical PCB variant. GPIO0 is BOOT with pull-up and button to ground. EN has datasheet-style pull-up/RC and RESET button. GPIO45/46 and module flash/PSRAM-reserved pins are not assigned. USB D-/D+ use native module GPIO19/GPIO20. Encoder A/B/push use RTC-capable, non-strapping GPIOs with RC filters. RGB data has a pulldown for safe/off boot behavior. ### PoE input and isolated power Silvertel AG9905-MTB isolated IEEE 802.3af PD/DC-DC module, nominal 5 V output, preserving primary/secondary isolation. Final PCB must enforce the module/RJ45 datasheet isolation keepout and creepage/clearance (Ag9900 datasheet §6: ≥3 mm clearance across the isolation barrier); shield/chassis treatment remains separate from logic GND. Input circuit per Ag9900 datasheet V3.5 (Figs. 5/14/16): jack P9/P10 (Mode B spare pairs) → bridge rectifier BR1 (MB4S/MB6S — required, pair polarity not guaranteed) → SMAJ58A tranzorb across VIN± (80 V surge ceiling) → module VIN+/VIN−. Mode A path (VA/BR2) unused — jack physically omits it. EMC per Fig. 16: MMZ2012S102A ferrites in VIN lines, 4.7 nF 2 kV Y-caps across the barrier; module targets EN55032 Class B pre-compliance. Output: C1 100 µF + C2 10 µF minimum. **⚠ OPEN ITEM — minimum load, needs a bench number.** The Ag9905 specifies a **200 mA minimum load** (datasheet §9.3); below it the DC/DC runs discontinuous and can emit **audible noise** (§2.3.3). The PoE variant is always-on, so this is less severe than a sleeping design: at the budget's "typical active" (~348 mA @ 3.3 V ≈ ~255 mA @ 5 V at 90% eff) the module is comfortably above minimum. The unproven state is **quiet idle** — ESP32 awake but idle, W5500 at link-idle (~15 mA), LED off — which is where the knob sits most of the time and which the budget table doesn't quantify. Resolve empirically at prototype bench: measure real idle draw at 5 V; if it falls below 200 mA, evaluate audible noise through a mounted wall plate and MPS stability, and only then decide whether any mitigation (small bleed, duty shaping) is needed. Full analysis in `si-46020-f-research-report`. ### Ethernet WIZnet W5500 SPI Ethernet controller with 25 MHz crystal network, reset, interrupt, CS pull-up, RBIAS, per-rail decoupling, and low-capacitance line protection. RJ45: **Stewart Connector / Bel SI-46020-F** (selected) — single-port **vertical (top-entry)** MagJack, through-hole, 10/100Base-T, AutoMDIX, **PoE**, shielded, green/green LEDs (570 nm, Vf 2.5 V max). Vertical entry chosen so the cable exits straight back into the box from the plate-mounted board. Verified from the Bel drawing (SI-46020-F rev C): body height above PCB **17.27 mm max**, face 16.51 × 17.27 mm max, pins ≤6.78 mm below board; 1500 VAC dielectric withstand; wave soldering recommended (260 °C / 10 s max). Beware siblings: SI-16001/16002/46001/46004/46014-F share the same mechanical package **without PoE** — the exact -46020 suffix matters. Replaces the earlier Pulse J0011D21BNL (horizontal) direction; magnetics terminations must follow the exact W5500 and **Bel SI-46020-F** reference circuits (Bob Smith termination is internal to the jack: 2×75 Ω + 1000 pF 2 kV to P7/chassis). **PoE is Mode B only, by construction and by intent.** Verified from the schematic: P9 carries power from J4/J5 (spare pair 4-5) and P10 from J7/J8 (spare pair 7-8), rated 400 mA max. Mode A is physically unavailable — the cable-side data-pair center taps terminate into the internal Bob Smith network, not pins. This matches the deployed infrastructure (Mode B injection only; Mode A is never used). **Recorded constraint**: a v2 board cannot power from a Mode-A-only PSE — if a future install feeds a knob directly from such a switch port, it will not power up; that is by design, not a fault. P9/P10 feed the AG9905 through its input bridge per the AG9905 reference circuit (bridge still required — pair polarity is not guaranteed). Depth stack (against the 2.5" / 63.5 mm worst-case box depth): PCB ~1.6 mm + jack 17.27 mm = ~19 mm verified; remaining ~44 mm must cover the plate→PCB standoff, the Cat6 plug's protrusion past the jack face, and cable exit bend. Plug protrusion is the largest unverified consumer — confirm with a physical measurement before finalizing. ### Battery charging and power path TI BQ24074 single-cell charger with dynamic power-path and TS input. Magnetic 5 V and USB 5 V are diode-ORed with independent Schottky paths so neither source backfeeds the other. A protected LiPo is required; board-side protection is recommended if the selected cell is not certified protected. TI TPS63802 2 A synchronous buck-boost regulates 3.3 V across the LiPo range. Battery voltage sensing uses a high-value divider switched by a GPIO so static drain is negligible when disabled. ### Expansion One compact 2×5 connector per variant: 3V3, GND, I2C SDA/SCL, SPI SCK/MOSI/MISO/CS, GPIO_A, GPIO_B. One pull-up pair only on I2C. SPI CS defaults high. ## Interfaces and Connections - USB-C receptacle: USB 2.0 D+/D-, CC1/CC2, VBUS, GND, shield. - Encoder: A, B, common, push contacts. - Expansion: 3V3/GND/I2C/SPI/two GPIO. - PoE: shielded RJ45 with integrated magnetics and PoE center-tap feeds. - Battery: keyed JST-PH 2-pin; 10 kΩ NTC sensing; exposed magnetic 5 V contacts. ## Power and Runtime Expectations - PoE variant is normally PoE-powered; USB is data/flashing and must not back-power the PoE output. - Battery variant supports simultaneous system operation and charging. - Battery design target: protected 1S LiPo, assumed 3000 mAh for preliminary runtime. - Firmware must keep the LED off by default on both variants. Battery variant: peripherals asleep except during interaction/update windows. PoE variant: always-on; no sleep requirement. ## Power Tree and Power Budget ### Preliminary 3.3 V rail budget | Load | Sleep/standby | Typical active | Peak/design | |---|---:|---:|---:| | ESP32-S3 Wi-Fi/module | 20 µA module assumption | 180 mA | 500 mA transient | | W5500 (PoE variant only) | 15 mA assumed link idle | 132 mA | 185 mA | | WS2812B-2020 | ~1 mA electronics assumption, power-gating not included | 10 mA | 60 mA full white | | Expansion allowance | 0 | 25 mA | 100 mA | | Encoder/pull networks | <10 µA static | <1 mA | 2 mA | | **Battery variant total** | **target <0.15 mA board-level** | **~216 mA** | **~662 mA** | | **PoE/Ethernet total** | n/a | **~348 mA** | **~847 mA** | The 500 mA ESP32 value is treated as a transient and is included simultaneously with peripheral maxima for conservative regulator/capacitor sizing. At 3.3 V, PoE-variant peak load is about **2.80 W**. Reflected to 5 V at 90% efficiency, required input is **~0.62 A**; add 30% margin -> design for **≥0.81 A**. The AG9905-MTB 5 V class module is therefore used with a 9 W-class budget, subject to final datasheet thermal derating. For the battery variant at depleted-cell **3.0 V**, 662 mA at 3.3 V and 85% worst-case conversion requires approximately **0.86 A battery input**. The regulator, inductor, connector, protection, and cell must each support at least this current; 1.2 A minimum design margin is targeted. ### Runtime assumption A 3000 mAh cell over seven days allows **17.9 mA average**. Preliminary duty model: 0.15 mA sleep infrastructure + 3.0 mA average for 60 s/hour Wi-Fi update at 180 mA + 2.2 mA average for 1% local active duty at 216 mA = **~5.35 mA average**, implying ~23 days ideal or ~16 days after 70% capacity/conversion/temperature derating. One week is feasible if firmware duty assumptions are met. Final validation requires measured sleep current and actual update duration/RSSI. ## Manufacturing and Assembly Expectations SMD production assembly with through-hole encoder/RJ45 as required. Every active part must retain a verified symbol/footprint. The PoE isolation boundary requires explicit copper/keepout review and safety/EMC review before production. Provide accessible rail, reset, boot, and programming test access during PCB stage. ## Firmware-Relevant Hardware Requirements - ESP-IDF OTA partition table sized for dual application slots within 16 MB flash. - Native USB via GPIO19/20; manual GPIO0 BOOT and EN RESET. - Wake-capable encoder inputs and push switch. - W5500 SPI with dedicated CS, interrupt, and reset. - I2C and SPI buses exposed on expansion connector. - Battery ADC divider enabled only for measurement. - Encoder decode must register **every physical detent 1:1** — no skipped/undercounted detents. Since v2 decodes quadrature directly on ESP32 GPIOs, this needs the chosen PEC11R pulse/detent ratio confirmed and A/B RC filter values that do not smear transitions at the fastest realistic spin speed. ## Physical Design Expectations Two separate all-in-one board shapes. PoE board uses a shielded integrated-magnetics vertical RJ45 with room for Cat6 plug body and bend radius in a US low-voltage box. ESP32 PCB antenna must face an enclosure edge with the Espressif keepout. Battery and magnetic contacts must be serviceable/protected in a screw-closed enclosure. PoE variant targets **standard US single-gang wall boxes** for **future installs**. **Design the PCB + RJ45 jack + connector stack to fit within the 2.5" worst case**. **Mounting**: the PCB is cantilevered off the wall plate entirely by the rotary encoder's own panel-mount bushing and nut. The encoder shaft location fixes where the rest of the board sits. The Cat6 plug is inserted once before the plate+board assembly is pushed into the box. The depth budget must include the RJ45 jack **with a plug permanently inserted plus its cable bend**. ## Important Design Decisions - No daughterboard architecture. - ESP32-S3-WROOM-1-N16R8 selected for 16 MB flash and 8 MB PSRAM. - AG9905-MTB selected to reduce isolated PoE prototype risk while retaining production-intent architecture. - W5500 selected for documented 100BASE-T SPI integration. - BQ24074 + TPS63802 selected for simultaneous charge/use and regulated 3.3 V over full 1S LiPo range. - PEC11R-4220F-S0024 selected as the v2 encoder: 24 detents / 24 PPR, push switch, 20 mm flatted shaft. Firmware quadrature divisor: 4 transitions per detent. - ESD TVS protection on encoder lines included. - Stewart/Bel SI-46020-F selected as the RJ45: vertical entry, 10/100, shielded, PoE **Mode B only** (spare pairs via P9/P10, 400 mA max; Mode A physically unavailable — accepted constraint matching Mode-B-only infrastructure). ## Assumptions - 3000 mAh protected LiPo; 3.0–4.2 V usable range. - USB-C ports operate as USB 2.0 sink/device, no USB PD negotiation. - USB source current is limited conservatively until firmware/hardware policy establishes advertised current. - Expansion peak allowance is 100 mA. - Final capacitor effective values must account for DC-bias derating. - PoE and Ethernet analog values remain subject to exact reference-circuit confirmation. ## Change Notes - Confirmed and documented SI-46020-F vertical MagJack selection. - Recorded deliberate Mode-B-only PoE constraint. - Added AG9905 bridge, surge, EMC, isolation, and 200 mA minimum-load requirements. - Preserved Cat6 plug/boot measurement as a physical validation gate before final placement.