PoE Schematic Audit

flux

The fork likely copied the design state but not this thread’s extraction context or downloadable report. I can restore it by adding the PoE recreation dataset and authoritative context to davidvivesprice/esp32-rotary-ui-controller-poe, then verify its schematic against the 79-component/65-net subset. Confirm that is the fork you want repaired.
purplerock

purplerock

Yes, restore the PoE recreation dataset and context in the fork, then verify its schematic matches the extracted subset.

flux

I’ll restore the extraction dataset and authoritative context in the PoE fork, then compare its schematic against the verified 79-component/65-net subset and report any mismatches.
Created a thread
Restore and verify PoE fork context
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flux

The restoration/verification thread for esp32-rotary-ui-controller-poe was launched and completed, scoped to modify project files only and leave the schematic untouched.
Open items
  • I could not retrieve and reconcile its final report because no ACUs remain.
  • The restored file links, verification totals, and any schematic mismatches still need confirmation.
Once ACUs are available, the next step is to read that completed thread’s results and independently confirm the fork against the 79-component/65-net reference subset.
Review restoration report
Verify schematic subset
Inspect project documents
Sign up to send

Files

Schematic

Layout

Preview

PoE Ethernet Completion Report
Completion Status
  • Completed: Worst-case PoE power budget and path sizing.
  • Completed: IEEE 802.3af Alternative A/B input, polarity bridges, surge clamp, isolated AG9905-MTB power conversion, output filter, and 3.3 V buck.
  • Completed: W5500 power, analog support, mode straps, SPI/control, oscillator, protected PHY pairs, MagJack LEDs, and exact NC/DNC/RSVD handling.
  • Completed: Focused connectivity/ERC review for the PoE/Ethernet scope.
  • Unattempted: PCB trace routing and formal safety/EMC certification; these are later layout/qualification stages.
Power Budget

Table

3.3 V loadPeak/design current
ESP32-S3 module transient500 mA
W5500185 mA
WS2812B-2020 full white60 mA
Expansion allowance100 mA
Encoder/pull networks2 mA
Total847 mA
  • 3.3 V peak power: 0.847 A × 3.3 V = 2.795 W.
  • 5 V input at 90% buck efficiency: 2.795 W / (5 V × 0.90) = 0.621 A.
  • With 30% margin: 0.621 A × 1.30 = 0.807 A; design target ≥0.81 A at 5 V.
  • An LDO would dissipate (5.0 - 3.3) × 0.847 = 1.44 W, above the 0.4 W threshold, so a buck converter is mandatory.
Selected Power Parts
  • U3 Silvertel AG9905-MTB: IEEE 802.3af Class 0, 36–57 V input, 1500 V impulse isolation, 5 V nominal. Datasheet ratings are 9 W / 1.8 A through 70 °C and 6 W / 1.2 A at 85 °C. Both exceed the 0.81 A design target.
  • U7 Diodes AP63203WU-7: fixed 3.3 V, 2 A synchronous buck, 3.8–32 V input. Support is the datasheet-recommended 3.9 µH inductor, 10 µF input capacitor, 2 × 22 µF output capacitors, and 100 nF BST-to-SW capacitor.
  • L3/C17/C18/C19: AG9905 Filter-B output network: 100 µF low-ESR mandatory output capacitor, 10 µF ceramic before and after a 1.8 µH filter inductor.
  • BR1/BR2: MB6S bridges for Alternative A and Alternative B polarity independence.
  • D8: SMAJ58A across the rectified PoE input, per Silvertel protection guidance.
RJ45 and Isolation Decision
The original Pulse J0011D21BNL was replaced. Its spare cable pairs 4/5 and 7/8 are internally terminated and not exposed as PoE input pins, so it could not implement the AG9905 dual-bridge Alternative A/B reference input.
The replacement Würth 7499210121A provides:
  • 100BASE-TX integrated 1:1 magnetics.
  • Data-pair center taps for Alternative A.
  • Separate spare-pair power terminals for Alternative B.
  • IEEE 802.3af support and 350 mA per center tap.
  • Green/yellow LEDs without assuming internal current limiting.
CHASSIS contains only J5 shield/mounting terminals. It is not joined to logic GND. POE_RECT_POS/POE_RECT_NEG remain on the cable/primary side of U3; U3 -VDC is the isolated secondary return and joins logic GND. PCB layout must preserve the AG9905 isolation keepout and at least 3 mm primary/secondary track clearance.
W5500 Implementation
  • All six AVDD pins and the VDD pin connect to 3V3_POE, each with a dedicated 100 nF capacitor (C24–C30); C31 adds 10 µF local bulk.
  • All AGND/GND pins connect to logic GND.
  • EXRES1: R31 = 12.4 kΩ, 1% to GND.
  • TOCAP: C32 = 4.7 µF to GND.
  • 1V2O: C33 = 10 nF to GND only.
  • VBG is intentionally floating.
  • PMODE2/1/0 are explicitly pulled high by R32/R33/R34, selecting 111: all capable, auto-negotiation enabled.
  • SPI connects to SPI_SCK_POE, SPI_MOSI_POE, and SPI_MISO_POE.
  • CS is pulled high; reset is pulled high with a 100 nF RC; IRQ is biased high.
  • Y1 is 25 MHz, 12 pF CL. C34/C35 are 20 pF C0G: C = 2 × (12 pF - 2 pF estimated stray) = 20 pF.
  • D3 ESD224 is inserted channel-by-channel between W5500 TX/RX pins and the MagJack PHY-side pins; its ground pins connect to logic GND.
  • Green RJ45 LED = LINKLED, yellow RJ45 LED = ACTLED, each with 330 Ω anode current limiting to 3.3 V. SPDLED and DUPLED are intentionally no-connect.
  • DNC pin 7, NC pins 12/13/46/47, RSVD pins 38–42, and permitted floating outputs are explicitly handled per the W5500 datasheet. RSVD pin 23 is tied to GND as required.
ESP32 GPIO Assignments

Table

FunctionESP32-S3 GPIONet
W5500 CSGPIO10W5500_CS_POE
W5500 IRQ, active lowGPIO17W5500_IRQ_POE
W5500 reset, active lowGPIO18W5500_RESET_POE
SPI SCKGPIO12SPI_SCK_POE
SPI MOSIGPIO11SPI_MOSI_POE
SPI MISOGPIO13SPI_MISO_POE
GPIO10/17/18 were previously reserved for variant work and are non-strapping pins. Existing shared-core assignments remain unchanged.
Created Nets
Power/isolation: POE_ALT_A_CT_TX, POE_ALT_A_CT_RX, POE_ALT_B_POS_PAIR, POE_ALT_B_NEG_PAIR, POE_RECT_POS, POE_RECT_NEG, 5V_POE_RAW, 5V_POE, POE_BUCK_SW, POE_BUCK_BST, CHASSIS.
W5500 control/support: W5500_CS_POE, W5500_IRQ_POE, W5500_RESET_POE, W5500_EXRES, W5500_TOCAP, W5500_1V2O, W5500_PMODE0, W5500_PMODE1, W5500_PMODE2, W5500_XI, W5500_XO.
Ethernet analog/LED: ETH_TXP_PHY, ETH_TXN_PHY, ETH_RXP_PHY, ETH_RXN_PHY, ETH_TXP_MAG, ETH_TXN_MAG, ETH_RXP_MAG, ETH_RXN_MAG, RJ45_GREEN_A, RJ45_YELLOW_A, RJ45_LINK_LED, RJ45_ACTIVITY_LED.
The Ethernet analog nets carry 100 Ω differential-pair metadata on both sides of D3.
Verification Evidence
  • Focused ERC/passive review shows no open PoE/Ethernet-scope errors. The remaining full-project electrical errors are exclusively the intentionally unwired battery charger/regulator block (U5/U6/J6/J7/D4/D5/TH1).
  • Connectivity inspection confirms USB_VBUS_POE contains only J1 and D1 VBUS-reference pins; it is not connected to 5V_POE, 5V_POE_RAW, or 3V3_POE.
  • 3V3_POE and 3V3_BAT have disjoint component memberships. CHASSIS contains only J5 shield terminals.
  • Physical checks report no open missing-footprint, outside-board, body-overlap, or overlapping-copper findings after scoped placement.
Justified Remaining Warnings / Follow-Up
  • Schematic symbols remain on automatically generated canvas positions because no schematic-arrangement mutation is available; electrical grouping is expressed through functional groups and named nets.
  • The placement optimizer left some proximity/loop-area advisory findings for local capacitors. These require final manual placement refinement during the PCB layout stage, before routing.
  • The AG9905 datasheet specifies a 200 mA minimum 5 V load to avoid audible discontinuous-mode noise and potential Maintain Power Signature issues. The expected active PoE controller load exceeds this; firmware should not place the entire PoE variant into an ultra-low-power state without validating PSE MPS behavior.
  • Final production sign-off still requires isolation keepout/creepage review, surge/ESD validation, controlled-pair routing review, thermal testing in the wall-box enclosure, and EMC testing.

  • Completion Status

  • Power Budget

  • Selected Power Parts

  • RJ45 and Isolation Decision

  • W5500 Implementation

  • ESP32 GPIO Assignments

  • Created Nets

  • Verification Evidence

  • Justified Remaining Warnings / Follow-Up