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Worked for 45 sec

An old out-of-credit routing job is blocking a new route run, so I’m discarding that stale job and starting a fresh route.

Worked for 33 mins 1 sec

flux

Auto-route reduced airwires from 53 to 9, but DRC still reports 9 airwires plus copper/trace issues. I’m running one more routing pass to try to finish the remaining connections.

Worked for 26 mins 10 sec

flux

Routing improved, but RUN/GND verification found RUN split and some reset pins still on GND. I’m correcting that now before wrapping up.

Worked for 2 mins 41 sec

flux

I re-routed using the active 6-layer stackup: fixed the auto-positioned TP pad blockers, reduced trace width for U1 fine-pitch routing, cancelled the stale out-of-credit route job, and ran two routing passes. Airwires improved from 53 → 9, but the router left 9 airwires, 3 overlapping-copper errors, and 22 dangling-trace warnings.

Open items:

RUN/GND connectivity is not clean: verification shows the RUN-side reset pins are still in a separate 12-pin net labeled GND despite repeated attempts to move them to RUN. I escalated this as a platform/data-repair issue.
Remaining DRC: 9 airwires, 3 overlapping-copper errors, 22 dangling-trace warnings.
Auto-route preflight still reports a duplicate-via cleanup warning.

Suggested next steps:

Repair the RUN net manually or via project history/data repair before manufacturing.
Re-run ERC on SW_RESET, U1:RUN, R_RUN:P1, C_RUN:P1, and J7:6.
Manually clean the 3 overlapping-copper errors, then route the final 9 airwires.

Fix RUN, copper, DRC

Fix RUN net

Inspect commit diff

Clean DRC errors

Manual final routing

Files

Schematic

Layout

3D View

Project Specification — RP2350 Dual-Port SAS USB Interface

Project Overview

Status: Draft. USB-C powered RP2350A board for dual independent SAS 9-bit serial ports used with casino gaming machines.

Intended Use

Prototype/production-intent interface board for development, diagnostics, host/responder emulation, and passive monitoring of two SAS ports.

What the Device Should Do

Enumerate over USB as a driverless vendor-class/WinUSB device.
Run RP2350 PIO-based 9-bit SAS serial on two independent ports.
Support host, EGM responder, and monitor modes per port.
Provide opto-isolated current-loop front-end as preferred population option and non-isolated RS-232 as alternate option.

Main Features

RP2350A QFN-60, external QSPI flash, 12 MHz crystal, SWD, BOOTSEL/reset controls.
USB-C 2.0 device input with CC pulldowns and USB data ESD.
+5V USB input, AP2112K 3.3V rail, TPS61040-derived 9V boost feeding VCC10 through Schottky OR.
Two Phoenix 4-pin SAS terminal connectors.
Per-port cable VCC ADC sense, status LEDs, mode straps, logic analyzer, SWD, and expansion headers.

System Architecture

Diagram

Hardware Subsystems

MCU: RP2350A with QSPI flash, crystal, reset/RUN/BOOTSEL, SWD.
USB: USB4105-GF-A USB-C receptacle, 5.1k CC pulldowns, USBLC6-2SC6 ESD array.
Power: AP2112K-3.3 for logic, TPS61040 boost to 9V, three 1N5817 Schottky sources to VCC10.
Front-ends: 6N139 optocouplers and SN7407 open-collector TX LED driver; MAX3232 RS-232 populate option per port.
Diagnostics: ADC dividers, cable live LEDs, firmware status LEDs, logic analyzer and expansion headers.

Interfaces and Connections

USB-C: VBUS, GND, D+, D-, CC1, CC2.
Port A/B screw terminal: Pin 1 GND, Pin 2 RX board-listens, Pin 3 TX board-transmits, Pin 4 cable VCC.
SWD: SWDIO, SWCLK, RUN/reset, 3V3, GND.
Logic analyzer: Port A/B TX/RX and GND.
Expansion: GPIO15–24 and GPIO28.

Power Tree and Power Budget

USB VBUS is +5V input and only host data link.
+3.3V from AP2112K-3.3 powers MCU, QSPI flash, logic-side front ends, transceivers, and LEDs.
VCC10 is supplied by diode-OR from Port A cable VCC, Port B cable VCC, or TPS61040 boost set to 9V.
Preliminary budget: RP2350 + flash + logic/front-end + LEDs expected within AP2112K 600mA if not all LEDs at high current; opto LED current is sourced from VCC10, not 3.3V.

Firmware-Relevant Hardware Requirements

Fixed GPIO map: GP0 A_TX, GP1 A_RX, GP2 A_TX_LED, GP3 A_RX_LED, GP4 A_HOST_LED, GP5 A_EGM_LED, GP6 B_TX, GP7 B_RX, GP8 B_TX_LED, GP9 B_RX_LED, GP10 B_HOST_LED, GP11 B_EGM_LED, GP12 mode strap A, GP13 mode strap B, GP14 reset/soft boot, GP25 heartbeat, GP26 ADC0 cable A VCC, GP27 ADC1 cable B VCC, GP15–24 and GP28 expansion.

Manufacturing and Assembly Expectations

SMD MCU and support circuitry; through-hole screw terminals for field wiring.
Populate options distinguish opto-isolated current-loop versus RS-232 front-end.
Use test points for +3V3, +5V, VCC10, boost switch-node, and GND.

Physical Design Expectations

Assumption: 4-layer rectangular PCB sized around the terminal blocks and USB-C connector, with USB at one edge and port A/B terminals at the opposite/front edge.

Important Design Decisions

Cable VCC dominates VCC10 when at or above 9V; boost supports bench mode only.
Opto interface is preferred and galvanically isolated; RS-232 option shares MCU pins and connector footprint as a non-isolated SKU.
Pin map is fixed by firmware and must not be reassigned.

Assumptions

USB-C operates as sink/device only; no USB PD.
4-layer stackup is selected because of USB routing, QFN MCU, switching boost, and mixed isolated/non-isolated field wiring.
RS-232 and opto population options should not be populated simultaneously on the same port unless explicitly reviewed.

Change Notes

Initial specification created from user-provided requirements.

Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power Tree and Power Budget
Firmware-Relevant Hardware Requirements
Manufacturing and Assembly Expectations
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes