Gaming Hardware Concept
Worked for 1 min 13 sec
I’m blocked because your account has no available ACUs, so I can’t run any more layout or DRC cleanup tools right now.
Accomplished:
- Applied a 6-layer stackup attempt and an explicit 6-layer stackup definition.
- Cleared stale partial routing.
- Spread the U1/U2/U6 cluster and support passives for better BGA escape.
- Re-ran the router; it applied 884 routing nodes.
- USB signal-integrity checks queried for USB returned no matching issues, but final DRC is not clean.
Open items:
- Final DRC still shows 33 airwire errors.
- Final DRC also shows 67 invalid Smart Via layer errors, indicating the same stackup recognition issue remains: stackup inspection shows the new stackup name, but layout summary still reports 2 copper layers.
- Some USB1 routing airwires remain in the final DRC list.
Suggested next steps when ACUs are available:
- Resolve the stackup/copper-layer recognition issue first.
- Delete or remap invalid Smart Vias after the stackup is recognized correctly.
- Surgically route the remaining USB1, MCU power, UART, FlexSPI, and debug airwires.
- Run final DRC again before treating the PCB as manufacturing-ready.
Check ACU status
Fix stackup issue
List airwires
Remap Smart Vias
Refine this doc
Ask about this doc
PROX MCU Selection and Schematic Netlist
Status: Draft schematic capture source
Date: 2026-07-26
1. Decision Summary
Selected MCU: NXP MIMXRT1062DVJ6B
Selected USB PHY approach: use the two integrated i.MX RT1062 USB 2.0 high-speed PHYs. No external USB PHY is required for the selected architecture.
Why this wins for PROX:
- The design needs two simultaneous USB roles: host to CONTROLLER and device to CONSOLE.
- i.MX RT1062 provides two USB 2.0 OTG controllers with integrated PHYs.
- STM32H723VGT6 in LQFP100 is easier to assemble, but the package does not bond out the full ULPI interface needed for an external high-speed USB host PHY.
- PC configuration stays off the real-time USB path through a separate USB-UART bridge.
Recommended schematic direction:
Table
| Port | Function | Implementation |
|---|---|---|
| CONTROLLER | USB host / Type-C source | i.MX RT1062 USB_OTG1 host + current-limited VBUS switch |
| CONSOLE | USB device / Type-C sink | i.MX RT1062 USB_OTG2 device |
| PC | Configuration/debug/logs | CP2102N USB-UART bridge to LPUART2 |
| POWER | Dedicated 5 V input | USB-C sink-only input through eFuse, then 3.3 V buck |
2. MCU Comparison
Table
| Requirement | STM32H723VGT6 | NXP MIMXRT1062DVJ6B | Winner |
|---|---|---|---|
| CPU headroom | Cortex-M7, 550 MHz | Cortex-M7, 600 MHz | i.MX RT1062 slight edge |
| Simultaneous USB host + USB device | Possible only if full USB HS ULPI + USB FS path are usable | Native fit: USB_OTG1 + USB_OTG2 | i.MX RT1062 |
| USB PHYs | Internal FS/OTG pins plus HS ULPI option, but package matters | Two integrated high-speed USB PHYs | i.MX RT1062 |
| Package assembly | LQFP100 is prototype-friendly | 196-ball 12 x 12 mm 0.8 mm MAPBGA | STM32H723VGT6 |
| Flash/boot complexity | Internal flash | Requires external QSPI/FlexSPI boot flash | STM32H723VGT6 |
| Hardware risk | ULPI bus and pin bonding issue | BGA escape, boot flash, power sequencing | Mixed |
| PROX architecture fit | Rejected for this exact VGT6 package | Selected | i.MX RT1062 |
Critical STM32H723VGT6 Finding
The STM32H723 USB HS ULPI interface requires signals including:
- ULPI_D0..D7
- ULPI_CK
- ULPI_STP
- ULPI_DIR
- ULPI_NXT
For STM32H723, the datasheet maps:
Table
| ULPI Signal | STM32 Pin | LQFP100 Availability |
|---|---|---|
| ULPI_D0 | PA3 | Available |
| ULPI_CK | PA5 | Available |
| ULPI_STP | PC0 | Available |
| ULPI_DIR | PC2 | Not bonded as digital PC2 on LQFP100; only PC2_C analog pin exists |
| ULPI_NXT | PC3 | Not bonded as digital PC3 on LQFP100; only PC3_C analog pin exists |
| ULPI_D3 | PB10 | Available |
| ULPI_D4 | PB11 | Available |
| ULPI_D5 | PB12 | Available |
| ULPI_D6 | PB13 | Available |
| ULPI_D7 | PB5 | Available |
Because PC2 and PC3 digital pins are not available in LQFP100, STM32H723VGT6 is not suitable for PROX if the controller-facing port must be a robust external USB HS host through ULPI.
If the STM32 path is revisited, use a package where all ULPI pins are bonded out, such as an LQFP144/BGA variant, and pair it with Microchip USB3300-EZK-TR or USB3320C-EZK-TR.
3. Selected Core Parts
Table
| Designator | Function | Selected Part | Flux Library UID / Note |
|---|---|---|---|
| U1 | Main MCU | MIMXRT1062DVJ6B | 8c7b1c91-4285-4dae-adcb-df7272d2090b |
| U2 | USB-UART bridge | CP2102N-A02-GQFN28 | e495d62e-16de-4f84-abe9-6ed3c7f9bf71 |
| U3 | 5 V input eFuse | TPS259530DSGR | 0f950ea8-7e2e-45ab-8fe1-21153251ca10 |
| U4 | 5 V to 3.3 V buck | LMR50410Y3FQDBVRQ1 | 18cb0a4c-c8a0-4fe7-8fa7-406928e614ea |
| U5 | Controller VBUS power switch | TPS2553DDBVT | 0d1cf17e-51b7-433a-8e00-4199aa21b75e |
| U6 | QSPI boot flash | MX25R6435FM2IL0 | 25ed0b65-1f44-4839-8e9f-a9abb75324d9 |
| J1-J4 | USB-C receptacles | UJ20-C-H-G-SMT-2-P16-TR | 23ac33ba-5051-4c33-86f0-90090296a41a |
| D1-D4 | USB 2.0 ESD arrays | USBLC6-2P6 | 2109fed9-46d8-455f-ae77-d0108e8b0893 |
| Y1 | Main 24 MHz crystal | X322524MPB4SI / YSX321SL class | 04185ddb-7ae5-4da2-b30c-ab76fcb44d90 |
Notes:
- U1 is a BGA. This is electrically the cleaner architecture but requires a 4-layer minimum PCB and competent BGA assembly.
- U6 boot flash is mandatory because MIMXRT1062 has no internal user flash for firmware storage.
- Y1 load capacitors must be recalculated from the actual crystal load capacitance and measured PCB stray capacitance.
4. Top-Level Net Names
Table
| Net | Purpose |
|---|---|
| GND | Digital/system ground |
| SHIELD | USB connector shield / chassis reference; connect to GND through ESD/RC strategy at layout stage |
| PWR_VBUS_RAW | Raw 5 V from POWER USB-C connector |
| 5V_SYS | Protected system 5 V after input eFuse |
| 5V_CTRL_VBUS | Current-limited 5 V supplied to CONTROLLER port |
| 3V3_SYS | Main 3.3 V logic rail |
| VDD_SOC | i.MX RT1062 internal DCDC output / core rail |
| USB1_DP, USB1_DN | CONTROLLER USB data pair |
| USB2_DP, USB2_DN | CONSOLE USB data pair |
| PC_USB_DP, PC_USB_DN | PC-port USB data pair to CP2102N |
| PC_UART_TX_TO_MCU | CP2102N TXD to MCU RX |
| PC_UART_RX_FROM_MCU | MCU TX to CP2102N RXD |
| HOST_VBUS_EN | MCU control for controller VBUS switch |
| HOST_OC_N | Controller VBUS switch fault, active low |
| POR_B | i.MX reset input |
| BOOT_MODE0, BOOT_MODE1 | i.MX boot-mode straps |
| FLEXSPIA_* | Boot flash bus |
5. USB-C Connector Pin Common Mapping
Selected connector: UJ20-C-H-G-SMT-2-P16-TR.
USB 2.0 Type-C pin mapping:
Table
| Connector Pin | Signal |
|---|---|
| A1, B12, A12, B1 | GND |
| A4, B9, A9, B4 | VBUS |
| A5 | CC1 |
| B5 | CC2 |
| A6 | Dp1 |
| B6 | Dp2 |
| A7 | Dn1 |
| B7 | Dn2 |
| A8 | SBU1, NC for USB2-only |
| B8 | SBU2, NC for USB2-only |
For each USB 2.0-only port:
- Tie A6 and B6 together at the connector side as that port's D+ net.
- Tie A7 and B7 together at the connector side as that port's D- net.
- Keep D+/D- short, symmetric, and routed as a 90 ohm differential pair.
- Place the USBLC6-2P6 ESD array close to the connector.
6. Port-Level Schematic Netlist
6.1 J1 — CONTROLLER Port, USB Host / Type-C Source
Role: PROX acts as USB host. Attached controller is a USB device.
Table
| J1 Pin(s) | Net | Connection |
|---|---|---|
| A1, B12, A12, B1 | GND | System ground |
| Shell tabs | SHIELD | Chassis/shield strategy; tie to GND through layout-defined ESD/RC network |
| A4, B9, A9, B4 | 5V_CTRL_VBUS | From U5 OUT |
| A6, B6 | USB1_DP_CONN | Through D1 to USB1_DP |
| A7, B7 | USB1_DN_CONN | Through D1 to USB1_DN |
| A5 CC1 | J1_CC1 | R_J1_CC1 = 56 kΩ to 5V_CTRL_VBUS or 5V_SYS |
| B5 CC2 | J1_CC2 | R_J1_CC2 = 56 kΩ to 5V_CTRL_VBUS or 5V_SYS |
| A8, B8 | NC | SBU not used |
Controller host power switch U5: TPS2553DDBVT.
Table
| U5 Pin | Net | Connection |
|---|---|---|
| IN | 5V_SYS | Input from protected system 5 V |
| OUT | 5V_CTRL_VBUS | To J1 VBUS and U1 USB_OTG1_VBUS |
| EN | HOST_VBUS_EN | From U1 GPIO; active high |
| FAULT | HOST_OC_N | To U1 GPIO interrupt input; add 10 kΩ pull-up to 3V3_SYS |
| ILIM | R_U5_ILIM | 22.1 kΩ, 1%, to GND for about 1.16 A nominal current limit |
| GND / PAD | GND | Ground and thermal land |
Controller USB data:
Table
| Net | Connection |
|---|---|
| USB1_DP_CONN | J1 D+ pins to D1 I/O1 side |
| USB1_DN_CONN | J1 D- pins to D1 I/O2 side |
| USB1_DP | D1 protected side to U1 USB_OTG1_DP ball L8 |
| USB1_DN | D1 protected side to U1 USB_OTG1_DN ball M8 |
| 5V_CTRL_VBUS | To U1 USB_OTG1_VBUS ball N6 |
D1 USBLC6-2P6:
Table
| D1 Pin | Net |
|---|---|
| I/O1 pins 1,6 | USB1_DP path |
| I/O2 pins 3,4 | USB1_DN path |
| VBUS pin 5 | 5V_CTRL_VBUS |
| GND pin 2 | GND |
6.2 J2 — CONSOLE Port, USB Device / Type-C Sink
Role: PROX appears as a USB HID/accessibility/test device to the target host.
Table
| J2 Pin(s) | Net | Connection |
|---|---|---|
| A1, B12, A12, B1 | GND | System ground |
| Shell tabs | SHIELD | Chassis/shield strategy |
| A4, B9, A9, B4 | CONSOLE_VBUS | Sense-only 5 V from console host; do not tie to 5V_SYS |
| A6, B6 | USB2_DP_CONN | Through D2 to USB2_DP |
| A7, B7 | USB2_DN_CONN | Through D2 to USB2_DN |
| A5 CC1 | J2_CC1 | R_J2_CC1 = 5.1 kΩ to GND |
| B5 CC2 | J2_CC2 | R_J2_CC2 = 5.1 kΩ to GND |
| A8, B8 | NC | SBU not used |
Console USB data:
Table
| Net | Connection |
|---|---|
| USB2_DP | D2 protected side to U1 USB_OTG2_DP ball P7 |
| USB2_DN | D2 protected side to U1 USB_OTG2_DN ball N7 |
| CONSOLE_VBUS | To U1 USB_OTG2_VBUS ball P6 |
D2 USBLC6-2P6:
Table
| D2 Pin | Net |
|---|---|
| I/O1 pins 1,6 | USB2_DP path |
| I/O2 pins 3,4 | USB2_DN path |
| VBUS pin 5 | CONSOLE_VBUS |
| GND pin 2 | GND |
6.3 J3 — PC Port, USB-UART Configuration / Type-C Sink
Role: PC configuration, logs, firmware-update command channel. This port is not in the HID real-time path.
Table
| J3 Pin(s) | Net | Connection |
|---|---|---|
| A1, B12, A12, B1 | GND | System ground |
| Shell tabs | SHIELD | Chassis/shield strategy |
| A4, B9, A9, B4 | PC_VBUS | VBUS sense to U2 only; do not tie to 5V_SYS |
| A6, B6 | PC_USB_DP_CONN | Through D3 to PC_USB_DP |
| A7, B7 | PC_USB_DN_CONN | Through D3 to PC_USB_DN |
| A5 CC1 | J3_CC1 | R_J3_CC1 = 5.1 kΩ to GND |
| B5 CC2 | J3_CC2 | R_J3_CC2 = 5.1 kΩ to GND |
| A8, B8 | NC | SBU not used |
U2 CP2102N-A02-GQFN28:
Table
| U2 Pin | Net | Connection |
|---|---|---|
| D+ pin 4 | PC_USB_DP | From D3 protected USB D+ |
| D- pin 5 | PC_USB_DN | From D3 protected USB D- |
| VBUS pin 8 | PC_VBUS | USB attach/sense input |
| VDD pin 6 | 3V3_SYS | Self-powered 3.3 V supply |
| VREGIN pin 7 | 3V3_SYS | Tie to VDD when internal regulator is not used |
| TXD pin 26 | PC_UART_TX_TO_MCU | To U1 LPUART2_RX, ball M13 |
| RXD pin 25 | PC_UART_RX_FROM_MCU | From U1 LPUART2_TX, ball H13 |
| RTS pin 24 | PC_UART_RTS_N | To U1 LPUART2_CTS_B, ball J12 |
| CTS pin 23 | PC_UART_CTS_N | From U1 LPUART2_RTS_B, ball K10 |
| RSTb pin 9 | CP2102_RST_N | 1 kΩ pull-up to 3V3_SYS; optional MCU GPIO/reset pad |
| GND pins 3, center pad | GND | Ground |
| NC pin 10 | NC | Leave floating |
D3 USBLC6-2P6:
Table
| D3 Pin | Net |
|---|---|
| I/O1 pins 1,6 | PC_USB_DP path |
| I/O2 pins 3,4 | PC_USB_DN path |
| VBUS pin 5 | PC_VBUS |
| GND pin 2 | GND |
6.4 J4 — POWER Port, USB-C Sink-Only 5 V Input
Role: dedicated system power input. No USB data required.
Table
| J4 Pin(s) | Net | Connection |
|---|---|---|
| A1, B12, A12, B1 | GND | System ground |
| Shell tabs | SHIELD | Chassis/shield strategy |
| A4, B9, A9, B4 | PWR_VBUS_RAW | Raw 5 V input to eFuse U3 IN |
| A6, B6 | NC | D+ unused |
| A7, B7 | NC | D- unused |
| A5 CC1 | J4_CC1 | R_J4_CC1 = 5.1 kΩ to GND |
| B5 CC2 | J4_CC2 | R_J4_CC2 = 5.1 kΩ to GND |
| A8, B8 | NC | SBU not used |
D4 USBLC6-2P6 is optional on POWER if D+/D- are not routed. For VBUS-only protection use a dedicated 5 V TVS diode near J4 instead. If D4 is installed anyway, leave I/O pins unpopulated/NC and use a separate VBUS TVS.
7. Main MCU Pin Assignment — MIMXRT1062DVJ6B
Package: 196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch.
7.1 USB Pins
Table
| Function | U1 Signal | Ball | Net |
|---|---|---|---|
| CONTROLLER USB D+ | USB_OTG1_DP | L8 | USB1_DP |
| CONTROLLER USB D- | USB_OTG1_DN | M8 | USB1_DN |
| CONTROLLER VBUS sense/supply | USB_OTG1_VBUS | N6 | 5V_CTRL_VBUS |
| CONSOLE USB D+ | USB_OTG2_DP | P7 | USB2_DP |
| CONSOLE USB D- | USB_OTG2_DN | N7 | USB2_DN |
| CONSOLE VBUS sense | USB_OTG2_VBUS | P6 | CONSOLE_VBUS |
| USB charger detect | USB_OTG1_CHD_B | N12 | NC for this revision |
7.2 PC Control UART — LPUART2
Table
| Function | U1 Pad | Ball | Peripheral | Net | Connects To |
|---|---|---|---|---|---|
| MCU UART TX | GPIO_AD_B1_08 | H13 | LPUART2_TX ALT2 | PC_UART_RX_FROM_MCU | U2 RXD pin 25 |
| MCU UART RX | GPIO_AD_B1_09 | M13 | LPUART2_RX ALT2 | PC_UART_TX_TO_MCU | U2 TXD pin 26 |
| MCU UART CTS | GPIO_AD_B1_06 | J12 | LPUART2_CTS_B ALT2 | PC_UART_RTS_N | U2 RTS pin 24 |
| MCU UART RTS | GPIO_AD_B1_07 | K10 | LPUART2_RTS_B ALT2 | PC_UART_CTS_N | U2 CTS pin 23 |
7.3 Power-Control GPIO
Table
| Function | U1 Pad | Ball | GPIO | Net | Notes |
|---|---|---|---|---|---|
| Host VBUS enable | GPIO_AD_B1_00 | J11 | GPIO1_IO16 | HOST_VBUS_EN | Drives U5 EN high to enable controller VBUS |
| Host overcurrent input | GPIO_AD_B1_01 | K11 | GPIO1_IO17 | HOST_OC_N | Active-low fault from U5, pull up to 3V3_SYS |
| Status LED 0 | GPIO_AD_B1_02 | L11 | GPIO1_IO18 | LED_STATUS0 | Optional |
| Status LED 1 | GPIO_AD_B1_03 | M12 | GPIO1_IO19 | LED_STATUS1 | Optional |
| Mode button | GPIO_AD_B1_04 | L12 | GPIO1_IO20 | BTN_MODE_N | Optional pull-up to 3V3_SYS |
| CP2102 reset | GPIO_AD_B1_05 | K12 | GPIO1_IO21 | CP2102_RST_N_DRV | Optional open-drain reset control |
7.4 Debug / JTAG / SWD Header
Use a 10-pin Cortex-style debug header or Tag-Connect equivalent. i.MX RT1062 supports JTAG/SWD-style debug through the SJC/JTAG pins.
Table
| Debug Signal | U1 Pad | Ball | Net | External Connection |
|---|---|---|---|---|
| JTAG_TMS / SWDIO | GPIO_AD_B0_06 | E14 | DBG_TMS_SWDIO | Debug header pin |
| JTAG_TCK / SWCLK | GPIO_AD_B0_07 | F12 | DBG_TCK_SWCLK | Debug header pin |
| JTAG_MOD | GPIO_AD_B0_08 | F13 | DBG_MOD | 1 kΩ pull-down to GND; optional header access |
| JTAG_TDI | GPIO_AD_B0_09 | F14 | DBG_TDI | Debug header pin |
| JTAG_TDO / SWO | GPIO_AD_B0_10 | G13 | DBG_TDO_SWO | Debug header pin |
| JTAG_TRSTB | GPIO_AD_B0_11 | G10 | DBG_TRST_N | Optional pull-down footprint; debug header pin |
| POR_B | POR_B | M7 | POR_B | Reset button + debug header reset |
| 3.3 V reference | — | — | 3V3_SYS | Debug header VTREF |
| Ground | — | — | GND | Debug header ground |
Important debug rules:
- Do not repurpose these pins in revision A.
- Keep JTAG_MOD pulled low for normal debug operation.
- Provide access to POR_B on the debug header and a physical reset button.
7.5 Boot Configuration
Table
| Function | U1 Pad | Ball | Net | Default Strap |
|---|---|---|---|---|
| BOOT_MODE0 | GPIO_AD_B0_04 | F11 | BOOT_MODE0 | 10 kΩ pulldown to GND |
| BOOT_MODE1 | GPIO_AD_B0_05 | G14 | BOOT_MODE1 | 10 kΩ pullup to 3V3_SYS |
Default target: internal boot from external FlexSPI/QSPI flash. Add 2-pin jumper or test pads so BOOT_MODE0/1 can be overridden for serial downloader recovery.
Boot-config pins sampled at reset should not be loaded by LEDs or noisy external circuits.
7.6 FlexSPI Boot Flash
U6 MX25R6435FM2IL0 to U1 FlexSPI A.
Table
| U6 Flash Pin | U6 Function | Net | U1 Pad | U1 Ball | U1 Function |
|---|---|---|---|---|---|
| 1 | CS# | FLEXSPIA_SS0_N | GPIO_SD_B1_06 | L3 | flexspi.A_SS0_B ALT1 |
| 2 | SO/SIO1 | FLEXSPIA_DATA1 | GPIO_SD_B1_09 | N4 | flexspi.A_DATA[1] ALT1 |
| 3 | WP#/SIO2 | FLEXSPIA_DATA2 | GPIO_SD_B1_10 | P4 | flexspi.A_DATA[2] ALT1 |
| 4 | GND | GND | — | — | Ground |
| 5 | SI/SIO0 | FLEXSPIA_DATA0 | GPIO_SD_B1_08 | P3 | flexspi.A_DATA[0] ALT1 |
| 6 | SCLK | FLEXSPIA_SCLK | GPIO_SD_B1_07 | L4 | flexspi.A_SCLK ALT1 |
| 7 | HOLD#/RESET#/SIO3 | FLEXSPIA_DATA3 | GPIO_SD_B1_11 | P5 | flexspi.A_DATA[3] ALT1 |
| 8 | VCC | 3V3_SYS | — | — | 3.3 V |
Recommended boot-flash passives:
Table
| Component | Value | Connection |
|---|---|---|
| R_FLASH_CS_PU | 10 kΩ | FLEXSPIA_SS0_N to 3V3_SYS |
| R_FLASH_WP_PU | 10 kΩ | FLEXSPIA_DATA2 to 3V3_SYS |
| R_FLASH_HOLD_PU | 10 kΩ | FLEXSPIA_DATA3 to 3V3_SYS |
| R_FLASH_CLK_SER | 22 Ω optional | In series with FLEXSPIA_SCLK near U1 |
| C_FLASH_DEC | 100 nF | U6 VCC to GND, close to U6 |
8. Power Delivery Netlist
8.1 USB-C POWER Input and 5 V System Rail
U3 TPS259530DSGR input eFuse.
Table
| U3 Pin | Net | Connection |
|---|---|---|
| IN pins 3,4 | PWR_VBUS_RAW | From J4 VBUS pins |
| OUT pin 5 | 5V_SYS | Protected system 5 V output |
| EN/UVLO pin 2 | EFUSE_EN_UVLO | Divider from PWR_VBUS_RAW to GND; set UVLO around 4.4 V for USB 5 V operation |
| dVdt pin 1 | EFUSE_DVDT | C_DVDT to GND for controlled inrush, start with 3.3 nF |
| ILM pin 7 | EFUSE_ILM | R_ILM to GND; size for total system current target |
| FLT pin 6 | EFUSE_FLT_N | 10 kΩ pull-up to 3V3_SYS; optional MCU GPIO |
| GND pin 8 and pad | GND | Ground and thermal pad |
Recommended input protection:
Table
| Component | Value / Type | Connection |
|---|---|---|
| D_PWR_TVS | 5 V VBUS TVS | PWR_VBUS_RAW to GND near J4 |
| C_PWR_IN1 | 10 µF | PWR_VBUS_RAW to GND near U3 |
| C_PWR_IN2 | 100 nF | PWR_VBUS_RAW to GND near U3 |
| C_5V_SYS | 22 µF | 5V_SYS to GND after U3 |
8.2 3.3 V System Buck
U4 LMR50410Y3FQDBVRQ1 fixed 3.3 V buck regulator.
Table
| U4 Pin | Net | Connection |
|---|---|---|
| VIN pin 5 | 5V_SYS | Input rail |
| GND pin 2 | GND | Ground |
| EN pin 4 | 5V_SYS | Tie high for always-on 3.3 V, or use divider for UVLO |
| SW pin 6 | BUCK_SW | To inductor L_BUCK |
| CB pin 1 | BUCK_CB | 100 nF bootstrap capacitor to BUCK_SW |
| FB pin 3 | 3V3_SYS | Fixed-output feedback sense point |
Recommended buck passives from datasheet:
Table
| Component | Value | Connection |
|---|---|---|
| C_BUCK_IN | 2.2 µF + 100 nF | 5V_SYS to GND, close to U4 |
| L_BUCK | 3.3 µH | BUCK_SW to 3V3_SYS |
| C_BUCK_BOOT | 100 nF | U4 CB to U4 SW |
| C_BUCK_OUT | 10 µF / 10 V minimum | 3V3_SYS to GND, close to inductor/output |
8.3 i.MX RT1062 Core and I/O Rails
The i.MX RT1062 internal DCDC is used for the core rail. Validate this subcircuit against the NXP i.MX RT1060 Hardware Development Guide before PCB release.
Table
| U1 Supply / Ball(s) | Net | Connection |
|---|---|---|
| DCDC_IN L1, L2 | 3V3_SYS | DCDC input |
| DCDC_IN_Q K4 | 3V3_SYS | DCDC input quiet supply |
| DCDC_GND N1, N2 | GND | DCDC ground |
| DCDC_LP M1, M2 | DCDC_SW | To 4.7 µH DCDC inductor |
| DCDC_SENSE J5 | VDD_SOC | Sense core rail after inductor |
| VDD_SOC_IN F6, F7, F8, F9, G6, G9, H6, H9, J9 | VDD_SOC | Core supply from DCDC output |
| DCDC_PSWITCH K3 | DCDC_PSWITCH | RC delay from 3V3_SYS; target 5-15 ms |
| VDD_HIGH_IN P12 | 3V3_SYS | High-voltage analog/internal regulator input |
| VDD_SNVS_IN M9 | 3V3_SYS | SNVS supply; tie to main 3.3 V if no coin cell |
| NVCC_GPIO E9, F10, J10 | 3V3_SYS | GPIO bank supply |
| NVCC_SD1 K5 | 3V3_SYS | FlexSPI boot flash bank supply |
| NVCC_SD0 J6 | 3V3_SYS | SD/GPIO bank supply if used |
| VDDA_ADC_3P3 N14 | 3V3_A | ADC analog supply, from 3V3_SYS through ferrite/filter |
| NVCC_PLL P10 | VDD_SOC / filtered PLL rail | Confirm exact rail with NXP HDG before layout |
| *_CAP pins: VDD_HIGH_CAP P8, VDD_SNVS_CAP M10, VDD_USB_CAP K8 | Local capacitors only | Do not externally drive; add caps per NXP HDG |
| VSS balls | GND | All ground balls to solid ground plane |
DCDC passives:
Table
| Component | Value | Connection |
|---|---|---|
| L_DCDC | 4.7 µH | DCDC_LP to VDD_SOC |
| C_DCDC_OUT | 33 µF | VDD_SOC to GND |
| C_SOC_DECOUPLING | Multiple 100 nF + bulk | VDD_SOC pins to GND, close to U1 |
| R/C_DCDC_PSWITCH | RC delay, 5-15 ms | 3V3_SYS to DCDC_PSWITCH with capacitor to GND |
9. Clock Netlist
9.1 Main 24 MHz Crystal
U1 requires a 24 MHz main clock for SDK-compatible operation.
Table
| Component | Net | Connection |
|---|---|---|
| Y1 pin 1 | XTALI | U1 XTALI ball P11 |
| Y1 pin 3 | XTALO | U1 XTALO ball N11 |
| C_XTALI | To GND | Load capacitor from XTALI to GND |
| C_XTALO | To GND | Load capacitor from XTALO to GND |
Initial load-cap estimate:
- Use 12 pF to 18 pF capacitors only after calculating from the actual crystal CL and PCB stray capacitance.
- Keep crystal loop very short, with local ground guard and no high-speed traces under it.
9.2 RTC Crystal
RTC is optional for PROX revision A.
Table
| U1 Pin | Ball | Net | Recommendation |
|---|---|---|---|
| RTC_XTALI | N9 | RTC_XTALI | Tie to GND if no 32.768 kHz crystal is fitted |
| RTC_XTALO | P9 | RTC_XTALO | Leave NC if no RTC crystal is fitted |
10. Schematic Capture Checklist
Before turning this netlist into the actual schematic:
- Verify every U1 power rail and capacitor value against the NXP i.MX RT1060 Hardware Development Guide.
- Confirm the boot strap state for FlexSPI boot and add recovery jumpers for serial downloader mode.
- Confirm the exact 24 MHz crystal load-cap calculation.
- Use a 4-layer PCB minimum: L1 signal/components, L2 solid GND, L3 power, L4 signal.
- Keep USB pairs on L1 referenced to L2 GND and route as 90 ohm differential pairs.
- Keep PC USB physically separated from console/controller USB routing.
- Do not connect CONSOLE_VBUS or PC_VBUS into 5V_SYS.
- Put ESD arrays close to USB-C connectors, before long D+/D- trace runs.
- Add test points for PWR_VBUS_RAW, 5V_SYS, 5V_CTRL_VBUS, 3V3_SYS, VDD_SOC, POR_B, BOOT_MODE0/1, USB VBUS rails, and HOST_OC_N.
11. Open Engineering Risks
Table
| Risk | Impact | Mitigation |
|---|---|---|
| BGA escape and assembly | Prototype fabrication complexity | Use 4-layer minimum, preferably 6-layer if routing/power integrity is tight |
| i.MX RT power sequencing | Boot failure or damage | Validate against NXP hardware guide before schematic finalization |
| Console HID compatibility | Target host may reject generic HID | Validate with a PC host first, then supported target modes only |
| USB-C role behavior | Enumeration or attach issues | Keep port roles simple; use correct CC resistors and isolated VBUS domains |
| Boot flash signal integrity | Boot failure | Place U6 close to U1; series-damp SCLK; route tightly |
| USB latency | Missed report deadlines | Keep PC UART/logging outside real-time path; use DMA/interrupt priorities |
12. Final Selected Architecture
PROX revision A should proceed with:
- MIMXRT1062DVJ6B main MCU
- Integrated USB_OTG1 as CONTROLLER host
- Integrated USB_OTG2 as CONSOLE device
- CP2102N USB-UART bridge for PC configuration/logging
- Dedicated USB-C 5 V power input through TPS259530 eFuse
- LMR50410 fixed 3.3 V buck regulator
- TPS2553 current-limited switch for controller VBUS
- MX25R6435 QSPI flash for boot firmware
- 4-layer minimum controlled-impedance PCB
This is the cleanest electrical architecture for the PROX four-port USB-C concept while keeping the real-time HID path isolated from PC-side configuration and logging.
1. Decision Summary
2. MCU Comparison
Critical STM32H723VGT6 Finding
3. Selected Core Parts
4. Top-Level Net Names
5. USB-C Connector Pin Common Mapping
6. Port-Level Schematic Netlist
6.1 J1 — CONTROLLER Port, USB Host / Type-C Source
6.2 J2 — CONSOLE Port, USB Device / Type-C Sink
6.3 J3 — PC Port, USB-UART Configuration / Type-C Sink
6.4 J4 — POWER Port, USB-C Sink-Only 5 V Input
7. Main MCU Pin Assignment — MIMXRT1062DVJ6B
7.1 USB Pins
7.2 PC Control UART — LPUART2
7.3 Power-Control GPIO
7.4 Debug / JTAG / SWD Header
7.5 Boot Configuration
7.6 FlexSPI Boot Flash
8. Power Delivery Netlist
8.1 USB-C POWER Input and 5 V System Rail
8.2 3.3 V System Buck
8.3 i.MX RT1062 Core and I/O Rails
9. Clock Netlist
9.1 Main 24 MHz Crystal
9.2 RTC Crystal
10. Schematic Capture Checklist
11. Open Engineering Risks
12. Final Selected Architecture
