EEG BCI Drone Control PCB Design

flux

0:08

Work done
  • Built the main schematic around U1, U2, U3, U4, U5, U6, and U7.
  • Implemented the EEG front end with the six mapped channels through J2, RC input filtering, SRB1 mastoid reference, and BIAS routing.
  • Wired split analog and digital rails with named nets for +3V3_A, +3V3_D, AGND, DGND, VBAT_3V7, +5V, and -5V_AVSS.
  • Added ADS1299 support capacitors, ESP32 boot support around R11, R12, C16, and charger / bias support around R6, R13, and C7.
  • Set the layout to 80 x 60 mm with a 4-layer stackup and baseline board rules suitable for this mixed-signal design.
  • Updated the project name and description to match the implemented EEG BCI architecture.
Success criteria review
  • ✅ Core schematic blocks are present: EEG AFE, ESP32 control, LiPo input, charger, boost, inverter, split 3.3 V regulators, channel mapping, and named power domains.
  • ✅ Layout target was set to the required 80 x 60 mm with a 4-layer stackup, which is the right class of stackup for mixed-signal SPI plus multi-rail power integrity .
  • ✅ ESP32 boot handling follows the required pattern of GPIO0 pulled high by default and EN held high with RC support .
  • ❌ The board is not placement-complete inside the required floorplan. Current density is reported as critical on 80 x 60 mm, so the exact requested placement arrangement is not yet physically realized.
  • ❌ The schematic still needs one cleanup pass before it is fabrication-ready: some ERC floating pins remain, the MT3608 feedback divider still needs a final sanity correction, and several intentionally-unused pins should be tied off or explicitly left unconnected.
  • ❌ The BOM exists, but many generic passives still need production MPN assignment before manufacturing release, which is required during physical-constraints finalization .
Next steps I can continue with the final cleanup pass now: fix the remaining regulator/ground details, explicitly terminate unused ADS1299 and ESP32 pins, assign real MPNs to the generic passives, and then re-run ERC/DRC. After that, the next physical issue is that 80 x 60 mm is extremely tight for this component set, so I can either optimize placement aggressively within that size or help trim the design for routability.
Lock exact pin map
Specify electrode connectors
Set power rail details
Define layout constraints
22 days
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    Hybrid EEG BCI for Pluto X v1.1 thumbnail
    Hybrid EEG BCI for Pluto X v1.1 using ESP32-WROOM-32 and ADS1299-6PAG with LiPo charging, 5V boost, -5V analog rail, split 3.3V analog/digital regulators, six EEG channels, RC electrode protection, and 80x60mm mixed-signal PCB constraints.

    Properties

    Diagram
    


  
    
  
  
    
  























SPI and control



















LiPo 3.7V Battery
TP4056 Charger
VBAT Rail
MT3608 Boost node_5V
5V Rail
ICL7660 Inverter
-5V Rail
LM1117 3.3V Analog
LM1117 3.3V Digital
3.3V Analog
3.3V Digital
ADS1299 EEG AFE
ESP32 WROOM 32
EEG Electrodes
2.2k and node_1nF Input Filters
Bias and Reference Network
AGND
Star Ground
DGND

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