PCB Design for ADL5521 LNA
Worked for 6 mins 23 sec
I started the requested fixes, but the session ran out of credits during routing.
Completed in this session:
- Corrected the 4-layer stackup so inner layer 1 is now a GND reference plane for top-layer RF routing.
- Added explicit routing width options and a 0.45 mm trace-width target to the PCB nets as the 50 Ω RF routing baseline for this stackup.
- Ran pre-route validation:
- Board is valid for routing.
- Warnings were only same-net overlapping SMA ground pads, which are expected for the connector footprint.
- Started the auto-route job, but it paused due to insufficient credits.
Important status:
- The board is still not fully routed.
- The 23 reviews likely still include airwires/unrouted-net issues because routing did not complete.
- I could not re-run and fix the full review list after routing because the routing job stopped.
Remaining work:
- Resume/complete routing once credits are available.
- Re-run all 23 reviews.
- Fix any remaining DRC/SI/ERC issues.
- Confirm RF traces are actually routed as controlled 50 Ω geometry, not just labeled as 50 Ω.
- Add/verify GND via stitching around the RF path and ADL5521 exposed pad.
Review actionable errors
Fix unrouted nets
Check RF impedance
Add via stitching
Export DRC report
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.