PCB Design for ADL5521 LNA
Worked for 6 mins 23 sec
I started the requested fixes, but the session ran out of credits during routing.
Completed in this session:
- Corrected the 4-layer stackup so inner layer 1 is now a GND reference plane for top-layer RF routing.
- Added explicit routing width options and a 0.45 mm trace-width target to the PCB nets as the 50 Ω RF routing baseline for this stackup.
- Ran pre-route validation:
- Board is valid for routing.
- Warnings were only same-net overlapping SMA ground pads, which are expected for the connector footprint.
- Started the auto-route job, but it paused due to insufficient credits.
Important status:
- The board is still not fully routed.
- The 23 reviews likely still include airwires/unrouted-net issues because routing did not complete.
- I could not re-run and fix the full review list after routing because the routing job stopped.
Remaining work:
- Resume/complete routing once credits are available.
- Re-run all 23 reviews.
- Fix any remaining DRC/SI/ERC issues.
- Confirm RF traces are actually routed as controlled 50 Ω geometry, not just labeled as 50 Ω.
- Add/verify GND via stitching around the RF path and ADL5521 exposed pad.
Review actionable errors
Fix unrouted nets
Check RF impedance
Add via stitching
Export DRC report
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ADL5521 Reference Eval Board Notes
Source Files
- Datasheet: uploaded
ADL5521.pdf, Rev. C. - Gerber archive: uploaded ADI
ADL5521_a01809c_Gerber.zip.
Design Target
Replicate the Analog Devices ADL5521 evaluation board schematic and layout intent for a standard 50-ohm RF environment. The factory eval-board tuning from the datasheet is optimized around 1950 MHz.
ADL5521 Pin Connections
Table
| Pin | Name | Implemented Connection |
|---|---|---|
| 1 | VBIAS | To VPOS through R1 |
| 2 | RFIN | RF input matching network output |
| 3,4,5,6 | NIC | Marked no-connect per datasheet |
| 7 | RFOUT | RF output path and output/bias tuning node |
| 8 | VPOS | Bias supply, decoupled to GND, output match network |
| 9 | EPAD | Low-impedance GND plane; use stitched vias under exposed pad |
Factory 1950 MHz Component Values
Table
| Ref | Value | Package | Function |
|---|---|---|---|
| C1 | 1.6 pF | 0402 | Input RF match, high-Q MLCC recommended |
| C2 | 0 ohm | 0402 | RF input series jumper/placeholder |
| L1 | 1.0 nH | 0402/0403 | Input RF match, high-Q inductor recommended |
| L2 | 0 ohm | 0402/0403 site | Output/bias matching jumper |
| C3 | 1.0 nF | 0402 | VPOS shunt tuning capacitor, slider position 4 for ~1950/2000 MHz |
| C4 | DNP | 0402 | Alternate output/bias shunt tuning footprint |
| C5 | 100 nF | 0402 | VPOS bypass/decoupling |
| R1 | 1.3 k ohm | 0603 | Bias-current set resistor |
| R2 | 0 ohm | 0603 | VPOS series jumper |
Optional 5 V Overdrive Protection Variant
If operating at 5 V where input power can exceed the input compression point (~7 dBm), the datasheet recommends changing R2 to at least 8 ohm with 0.2 W minimum rating and reducing R1 to 600 ohm to keep supply current near 60 mA.
Layout Intent
- Use a controlled-impedance RF path for J1 -> input match -> ADL5521 RFIN and ADL5521 RFOUT -> J2.
- Keep RF traces short, direct, and referenced to an uninterrupted GND plane.
- Place SMA edge-launch connectors at opposite board edges with coax center pins aligned to the RF microstrip path.
- Place C1/L1 tightly at the RF input pin.
- Place C5 directly at VPOS with a short return to the exposed-pad/ground plane.
- Place C3/C4 footprints along the VPOS bias slider region so C3 can be moved for S22 tuning.
- Stitch the exposed pad to the GND plane with at least five vias, per datasheet land-pattern guidance.
Caveat
The uploaded Gerber archive did not expose parseable board-outline dimensions through the file reader in this session. The layout is therefore recreated from the datasheet schematic/layout intent, with a compact 4-layer controlled-impedance evaluation-board geometry rather than a direct Gerber import.
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