Power Entry Stage Design

flux

Work done
  • Refined PCB component placement only; no routing was performed.
  • Floorplanned the SAR board per the constraints file: RF chain left in order J3 → C19 → U7 → U8 → U6, U9 near U8, PLL filter parts beside U9, ADC center-left, FPGA centered, FT2232H/USB on the right, power along the top, and debug/test/LED/reset along the bottom.
  • Ran a focused cleanup pass to keep the crystal loop and power-entry/debug access from crowding while preserving the routing corridors.
Success criteria review
  • ✅ RF chain ordering and left-side RF isolation corridor are preserved.
  • ✅ PLL filter remains immediately beside U9, with U9 close to U8 for a short LO path.
  • ✅ U6 is center-left and ADC bus series parts are between U6 and U3 for a straight bus channel.
  • ✅ U3 remains centered with bus corridors preserved toward ADC on the left and FIFO/USB on the right.
  • ✅ U5 and J2 are grouped on the right with USB support/ESD nearby.
  • ✅ Power and debug sections are assigned to the top and bottom edges respectively.
  • ✅ Schematic connectivity was not changed and no PCB routing was created.
Next steps
  • Proceed with staged routing: RF first, then PLL/ADC clock, ADC bus, USB pair, FIFO bus, power, and finally debug/GPIO.
Run placement DRC
Tighten ADC corridor
Check unmet constraints
Export placement report
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Repulsive Red Dejarik thumbnail
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