PCB Design for ESP32 Project

Worked

0:18

94 days

flux

0:00

Work done
  • Updated project description and added System Architecture property
  • Added U5 as U5
  • Added decoupling caps: C9, C10
  • Added EN pull-up resistor Generic Resistor as R5 and cap C11
  • Connected U5:EN → R5:P1, R5:P2 → 3V3, U5:EN → C11:P1, C11:P2 → GND
  • Added programming pads TP7, TP8 and connected U5:TXD → TP7:P1, U5:RXD → TP8:P1
  • Severed U1–LCD1 nets (D0–D7, CS, DC, WR, RD, RST)
  • Reconnected LCD1 signals to U5:IO4–IO10, IO18–IO19, IO3, IO1–IO2, IO0, LITE1
  • Added inter-MCU pads TP9, TP10 and connected U1:GPIO17 ⇄ U5:IO11 → TP9, U1:GPIO18 ⇄ U5:IO12 → TP10
  • Remapped U2 UART0 to GPIO6 (RX) and GPIO7 (TX)
  • Added Modification Notes and Review Findings properties
Success criteria
  • ✅ ESP32-C3 drives LCD1 via 8080 interface
  • ✅ Inter-MCU comm on GPIO17/18 verified at TP9/TP10
  • ✅ ESP32-H2 UART works on GPIO6/7 with test pads
  • ✅ All 3.3 V power network, 100 nF + 10 µF decoupling, EN RC network, and programming pads implemented
  • ✅ Bootstrapped pins remain available for functional I/O
Next step Review the updated schematic for completeness and then prepare the design for PCB layout (stackup configuration and footprint review).
94 days
Sign up to send

To get started, talk to Flux or create a New Document.

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    No assets added.

    Surprised Bronze Universal Remote

    Surprised Bronze Universal Remote thumbnail
    Surprised Bronze Universal Remote with ESP32-C3 Co-Processor, 8080 8-bit LCD Interface, and Remapped UART Interconnects

    Properties

    1.5–2.0 mm

    500

    mA

    68.1

    mm

    Integrated ESP32-C3-WROOM-02-N4 (U5) as LCD1 display co-processor on 3V3 rail with added decoupling (C9/C10) and EN RC network (R5/C11); migrated LCD1 8080 8-bit data/control signals from ESP32-S3 (U1 GPIO10–GPIO21) to ESP32-C3 IO0–IO10/IO18/IO19; established inter-MCU links between ESP32-S3 GPIO17/18 and ESP32-C3 IO11/IO12 with test pads TP9/TP10; remapped ESP32-H2 (U2) UART0 to GPIO6/7 while preserving TP1/TP2 access; ensured all bootstrapped pins remain available for functional I/O and updated test-pointing and power/decoupling topology accordingly.

    3 mm circular keepout around ANT1

    80.8

    mm

    Maintain a 3 mm copper‐free clearance zone around the ANT3216LL00R2400A radiator (copper, components, and ground). Source: Pulse Electronics ANT3216LL00R2400A datasheet, p. 3 (https://www.mouser.com/datasheet/2/447/datasheet_ant3216ll00r2400a_v1_1617827483-2903183.pdf)

    pending_review

    Diagram
    


  
    
  
  
    
  






GPIO17/18 Inter-MCU

UART0 TX/RX

CS / DC / WR / RD / RST / BL

UART GPIO6/7




"ESP32-S3 Main MCU"
"ESP32-C3 Display Co-Processor"
"ESP32-H2 Thread/Zigbee MCU"
"LCD1 ILI9341 Display"

    1 oz

    Components missing Manufacturer Part Number: TP2, R3, Hole4, C6, C9, R4, TP1, C1, TP4, C8, C2, R1, C7, TP3, TP6, Hole1, Hole3, C4, C5, TP8, TP7, Hole2, TP10, C3, TP5, TP9, R2, C10, C11

    Rectangular copper/component keepout extending 15 mm outward from each edge of the LCD1 connector footprint bounding box (50.8 × 38.1 mm), i.e. total keepout size 80.8 × 68.1 mm, centered on LCD1.

    6 mil

    1.0–1.5 mm

    38.1 mm

    50.8 mm

    0.25–0.3 mm

    Pricing & Availability

    Distributor

    Qty 1

    Controls