I’ll inspect the schematic/netlist for unconnected power pins, map each IC/module power pin to the intended rails, apply the needed wiring fixes, then run validation to catch remaining power/ERC issues.
Initial inspection found the IC supply pins already assigned to the expected rails; I’m making one focused power-net cleanup pass on rail metadata and the relay coil return so the power intent is explicit.
Power-net review and wiring cleanup is complete. I marked the main rails as Power/Ground, verified U1/U2/U3/U4/U5 supply pins are connected to their expected rails, and connected K1/K2 relay coil NEG return to AGND.
Open items:
K1/K2 relay coils are now tied from +5V_RELAY to AGND, so they will be continuously energized unless you intended to add switching control.
Suggested next steps:
Add transistor/MCU relay drivers if the relays should be controllable.
Review decoupling capacitor placement near each IC power pin.
Proceed with layout/routing checks for the updated power nets.
Stereo high-end preamp based on the supplied modular structure. The signal path is input buffer → relay-selected tone module → MUSES72320 volume control → output buffer.
Functional Blocks
Input buffers for L/R line inputs
Relay A/B selection between analog tone IC path and ADAU1701 DSP tone path
MUSES72320 stereo volume control
Output buffers for L/R line outputs
MCU control for I2C/SPI, relays, encoder, and display
Linear ±15 V analog rails, 5 V rail, and filtered 3.3 V rail
Initial Assumptions
OPA2134 dual op-amps are used for line input/output buffers.
ADAU1701 is the DSP tone module candidate.
NJW1194/NJW1191 analog tone module remains selectable pending exact part availability/pinout.
MCU is initially represented by a practical development/embedded controller candidate until final UI/display choice is fixed.
Validation Targets
Confirm exact NJW tone-control part and package availability.
Verify MUSES72320 pinout and support circuitry from datasheet before final wiring.
Verify ADAU1701 clock, boot mode, decoupling, and analog front-end details.
Run ERC after schematic capture and resolve unintentional floating pins.