Schematic Completion Gaps
Fresh status check: 2026-08-20
Current design: 169 components, 168 nets.
Bottom line
The logical schematic is fully wired and the fresh ERC is clean, but it is not yet production-complete because sourcing metadata and power-stage validation remain open.
1. Unresolved or stale nets
Two empty net objects remain and should be deleted as cleanup:
+12V_FUSED — 0 connected pins.U1_GATE — 0 connected pins. The active gate-drive connection is correctly named GATE_DRV.
No connected single-pin nets, floating pins, undriven nets, or unconnected wire endpoints remain.
2. Unwired stages
None. All defined stages are represented and electrically connected:
- Power entry, +5 V and +3.3 V rails
- ATmega core and ESP32 orchestration
- Both W5500 Ethernet interfaces and magnetics/connectors
- F-RAM, RTC/CR2032, ATECC608B
- USB-C and service/debug paths
- SAS and both switched COM isolation paths
- J8/J9 optocoupled machine I/O
- LM5155 54 V boost and TPS23861 Mode-B PSE port
- J7 ISP/UART/power/test header
- ESP32 remote ATmega ISP/reset path
3. ERC and automated review status
Fresh electrical review returned zero ERROR, WARNING, OPEN, or UNCERTAIN findings for:
- Floating pins
- Single-pin nets
- No-connect handling
- Missing/undriven power pins
- Driver conflicts
- Pin-to-pin conflicts
- Shorted components
- Undriven nets
- Unconnected wire endpoints
- Annotation/label similarity and multi-unit consistency
Passive/component checks also have no open electrical findings. The missing-footprint check is clean.
4. Missing manufacturing MPNs — review count discrepancy
The manufacturing review category header reports 85 parts without an MPN, but the individual findings enumerate 88 designators: 24 resistors, 63 capacitors, and TP1. Use the enumerated designators as the actionable source and re-run the check after assignments. This does not break connectivity, but it blocks calling the BOM manufacturing-ready.
Resistors — 24
R1, R2, R3, R4, R6, R9, R10, R11, R12, R13, R14, R15, R16, R17, R19, R20, R68, R69, R70, R71, R72, R73, R74, R75
Capacitors — 63
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C60, C62, C63, C64, C65, C66, C67, C68, C69, C74, C75, C76, C77
Four LM5155 capacitors (C70-C73) already have exact reference-design MPNs and are intentionally excluded.
Test point — 1
Highest-priority sourcing selections
C74, C75: 4.7 µF, 100 V output ceramics with DC-bias-effective capacitance verified at 54 V.C76: 100 µF, 100 V low-ESR bulk output capacitor with adequate ripple-current rating.C77: 100 µF, 25 V input bulk capacitor with adequate ripple-current and hot-plug rating.C66, C69: 100 nF, 100 V X7R parts for TPS23861 VPWR/port use.R16, R17: 0.51 Ω, 1%, 0.25 W Kelvin shunt pair in 0805.TP1: assign the intended manufactured test-point MPN or explicitly mark as a copper-pad test feature excluded from BOM.
5. Newly confirmed component conflict
F2 response type
F2 = Littelfuse 045101.5MRL is rated 1.5 A and 125 V, so its voltage/current ratings are suitable. However, its datasheet identifies it as very fast-acting. The TPS23861 reference guidance calls for a slow-blow fuse rated at least 60 VDC and above approximately 2× ICUT(max).
This is a real datasheet conflict. Before release, either:
- Replace F2 with a 1.5 A-class, ≥60 VDC time-delay fuse, or
- Explicitly approve the very-fast fuse after inrush/startup testing proves nuisance opening will not occur.
6. Power-stage validation still required
The LM5155 circuit is adapted from TI's 24 V / 48 W reference to 54 V using a 106 kΩ / 2 kΩ feedback divider and 100 V switch/rectifier/output parts. It still requires validation across the approved 10.8–13.2 V ATX range:
- Startup and hot-plug behavior
- 54 V regulation and ripple
- Peak switch/inductor/shunt current
- Current-limit margin
- MOSFET, diode, inductor, and shunt temperature rise
- Output-capacitor ripple current and DC-bias derating
- Compensation/loop stability and transient response
- TPS23861 detection/classification/inrush with the selected PSE supply
This is a validation task, not an unwired schematic gap.
7. Explicit design choices awaiting review sign-off
- Q2: currently source=
USB_VBUS, drain=+5V, gate pulled to GND through R13=100 kΩ, creating automatic USB-powered +5 V with PMOS reverse blocking. This was intentionally flagged for review.
- D2/TP1: D2 cathode=
+5V, anode=TEST_CLAMP_NODE, with TP1 on the protected node. This was intentionally flagged for review.
Exact finish checklist
- Delete empty nets
+12V_FUSED and U1_GATE.
- Resolve F2 fast-acting versus required time-delay behavior.
- Assign the 88 individually enumerated missing MPNs, prioritizing high-voltage/high-current parts, then re-run the manufacturing check to resolve its 85-versus-88 count discrepancy.
- Approve or revise the Q2 and D2/TP1 review-note choices.
- Validate the LM5155/TPS23861 power stage electrically and thermally.
- Re-run ERC, passive/component checks, BOM review, and netlist/domain audit.
- Stop before PCB layout until those items pass.