PCB Placement Checkpoint
Scope status
- Completed — Board setup: Board resized to exactly 100 mm × 100 mm, rectangular, with JLC3313 4 Layer (Custom) stackup. L2 is a Ground Plane, L3 a Power Plane, outer layers are signal. Total thickness reported as 1.49 mm. A 0.25 mm universal placement keepout/inset is active.
- Completed — U2/U3 anchors: U2 and U3 were placed first as separate LMR33630 HSOIC islands using TI Rev F, SNVU573A, and SNVA951 guidance.
- Completed — Critical-region reservation: 12 V input/protection, LM5155 boost/TPS23861 PSE, Ethernet chains, isolated interfaces, USB, and ESP32 regions were placed before ordinary logic.
- Completed — Full placement: All 170 PCB elements are inside the board with zero component-body overlaps, zero keepout violations, and zero out-of-bounds elements.
- Completed — No routing: No traces were routed.
- Blocked — Routability certification: Physical placement is complete, but auto-route precheck found malformed/collapsed footprints on multiple existing parts; routing cannot safely begin until those footprints are repaired.
Board and stackup
- Dimensions: 100.00 mm × 100.00 mm
- Stackup: JLC3313 4 Layer (Custom)
- L1: Top signal/components
- L2: Continuous GND reference plane
- L3: Power plane / local low-speed planning
- L4: Bottom signal/components
- Vias: standard through-hole L1–L4, 0.6 mm pad / 0.3 mm drill
- Placement count: 149 top, 21 bottom
- Bottom-side parts are only small resistors/capacitors. All ICs, connectors, magnetics, inductors, power semiconductors, electrolytics, battery/service hardware remain top-side.
Connector edge assignments
- Top-left: JD downstream Ethernet + PoE output
- Top-right: J3 LAN Ethernet
- Left edge: J1 12 V input
- Right edge: J8 machine inputs, J9 machine outputs, J4/J5/J6 isolated serial connectors
- Bottom edge: J7 service/debug header and J2 USB-C
All connector bodies are within the outline and have outward cable-access space.
Critical placement regions
U2 island — lower-left
- U2 center: approximately (-31, -31) mm
- C2 is immediately at the VIN/PGND side.
- C4 is at VCC; C5 is at BOOT/SW.
- L1 is directly on the SW side with a reserved short switch-node corridor.
- C6/C7 are on the output side.
- R1/R2/C3 are on the quiet FB side, separated from SW.
- Exposed-pad access remains open for thermal vias and ground spreading.
U3 island — lower-left/center
- U3 center: approximately (-13, -31) mm
- C10 is immediately at VIN/PGND.
- C8 is at VCC; C9 is at BOOT/SW.
- L2 is directly on the SW side; C11 is on the output side.
- R3/R4 are on the FB side away from SW.
- The island has exposed-pad/thermal-via and heat-spreading space.
Boost/PSE region — upper-left and left-center
- Reserved contiguous region contains U29, L3, Q6, D4, U28, Q5, R21, R16/R17, F2, D3, C65–C77 and related R/C.
- L3/Q6/D4 form a compact boost power path.
- C76/C74/C75 are grouped on the 54 V output side; C77 is on the protected-input side.
- U29 small-signal parts are placed locally around the controller.
- U28, Q5, port shunts, fuse/TVS and bypass parts remain inside the same dedicated PSE region.
- Ordinary logic is kept outside this region; a physical corridor separates it from the central logic/isolated areas.
Domain strategy
- GND: Main power, logic, MCU, memory and Ethernet-control regions occupy the left/center and upper-right areas, referenced to the continuous L2 plane.
- ISO_GND: Isolated COM/SAS blocks are concentrated in a dedicated lower-right lane around U10–U16 and J4–J6, physically separated from main logic and power.
- CHASSIS: Chassis/shield-connected interfaces remain at board edges, particularly Ethernet and USB/machine-facing connectors, avoiding crowding into the isolated serial lane.
- The 54 V/PSE area is physically separated from unrelated logic and isolated regions. Final copper clearances must preserve the specified 0.6 mm minimum, preferably the planned ~1 mm corridor.
High-speed placement
- LAN path: U7 → T1 → J3 is direct and vertically organized at the top-right.
- Downstream path: U7B → T1B → JD is direct at the top-left.
- USB-C J2 is on the bottom edge with U6/Q2/support parts immediately inboard and an unobstructed D+/D− escape corridor.
- U5 is the external-antenna ESP32-S3-WROOM-1U-N16R8; no PCB-antenna overhang was created. It is placed near the bottom edge with RF connector access space.
Verification evidence
Fresh layout inspection reports:
- Aggregate component bounds: 98.71 mm × 98.87 mm, wholly inside the 100 mm × 100 mm outline
- Component-body overlaps: 0
- Out-of-bounds components: 0
- Keepout violations: 0
- Stackup: valid JLC3313-derived 4-layer configuration
- Airwire review: 666 expected unrouted connection checks; routing was intentionally deferred
The focused placement checks returned no open component-body-overlap, outside-board, missing-footprint, invalid-layer, keepout, pad-access, stackup, or edge-placement findings.
Remaining blocker: malformed existing footprints
The no-route auto-router precheck found 29 blocking DRC_OVERLAPPING_PINS_DIFFERENT_NETS anomalies. Direct layout inspection confirms that multiple existing project parts use a 1.6 mm × 1.6 mm placeholder footprint with every pad collapsed at the same coordinate. Confirmed examples include:
- U12 ADUM1201ARZ-RL7
- U14 MAX3232EIDR
- J8 0026604060
- X1 SX3B16.000F2010F30
- U23 PC817C
The same issue affects additional ICs, connectors, crystals, MOSFETs and optocouplers. The overlapping-copper review consequently reports hundreds of footprint-internal pad collisions. These are not inter-component placement overlaps and cannot be fixed by moving parts; the affected footprints must be repaired or replaced before routing.
100 mm × 100 mm viability
- Placement viability: Yes. The complete design fits safely in 100 mm × 100 mm with 149 top / 21 bottom components and no placement collisions.
- Routing viability: Conditional, not yet certifiable. The routing-aware fill is approximately 72.7%, so the board is dense but plausibly routeable on four layers with L2 continuous GND and L3 power planning. However, the current malformed footprints make the router discard pins and prevent a meaningful routeability result.
- No placement evidence currently justifies exceeding the 100 mm cost ceiling. After footprint repair, rerun the board precheck before routing; if congestion then proves limiting, the likely pressure points are the lower-right serial/USB lane and the upper-left Ethernet/boost/PSE boundary.