Hardware Prototype Planning

flux

Confirmed. This manufacturer-specified stackup is authoritative and supersedes the earlier standard-1-oz assumption:

Table

LayerFunctionCopper
TopSignal/components0.070 mm / 2 oz
Mid-Layer 1Solid GND plane0.035 mm / 1 oz
Mid-Layer 2Power plane0.035 mm / 1 oz
BottomSignal0.070 mm / 2 oz
I’ll use this for power-trace sizing, thermal calculations, pours, via-current capacity, and manufacturing checks. The board remains top-side assembly only; the bottom layer may still carry routed copper.
For Ethernet and USB pair geometry, copper thickness alone is insufficient—the manufacturer’s dielectric thicknesses and finished board thickness are also needed for an accurate impedance estimate. Since paid impedance control is intentionally omitted, routing will prioritize tight coupling, symmetry, continuous L2 ground reference, and minimal pair skew.
pinionseal44

pinionseal44

Top Copper 0.070mm 2oz Mid-Layer 1 Copper 0.035mm 1oz (Ground Plane) Mid-Layer 2 Copper 0.035mm 1oz (Power Plane) Bottom Copper 0.070mm 2oz name="custom-4-layer"

flux

Confirmed. The authoritative PCB stackup is:
custom-4-layer

Table

LayerRoleCopper thicknessWeight
TopSignal0.070 mm2 oz
Mid-Layer 1Ground plane0.035 mm1 oz
Mid-Layer 2Power plane0.035 mm1 oz
BottomSignal0.070 mm2 oz
Top-side-only assembly remains required; bottom-side copper routing is allowed.
Agent mode is needed to apply this stackup to the PCB and recalculate copper-dependent rules. Dielectric thicknesses can be added later if you obtain them; they are needed for an impedance estimate but do not block basic stackup configuration.
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Schematic

Layout

Preview

Manufacturing Closure Status
Date: 2026-08-21
Overall result
Overall task: incomplete / export blocked. The live project is materially improved and left in a safer top-only, non-overlapping placement state, but it is not routed and therefore is not fabrication-ready.
Scope status

Table

ItemStatusEvidence / remaining issue
Inspect live project and authoritative CSVCompletedLoaded the supplied 85-row CSV attachment. The previously referenced repository CSV was inaccessible, but the later attachment was readable.
BOM correctionsPartially completedApplied the required live corrections listed below. Much of the existing BOM was already aligned with the uploaded CSV, including the correct library parts for U8, U17 and U19-U26. A final exhaustive 85-row, designator-by-designator readback comparison was not completed in this time-box.
Top-side-only placementCompleted170 top, 0 bottom. No component body overlaps, no out-of-bounds components, and no keepout violations in the final placement pass.
Rotations/orientation normalizationPartially completedPlacement and several conflicting rotations were repaired, including Q3/Q4. A complete human mechanical mating-direction review of every connector was not finished.
Footprint/DFM repairPartially completedKey authoritative footprints and global manufacturing rules were applied. Integrated checks show no missing footprints, invalid layers, outside-board parts, body overlaps, or different-net copper overlaps. A fresh external JLCDFM scan was not run, and plated-slot widths were not exhaustively re-measured.
RoutingFailed / unattempted after cleanup361 airwires remain. No autoroute was started because the time-box ended after footprint/placement/preflight repair.
Final DRC/DFM release gateFailedAirwires remain; one ERC single-pin net remains; one routing-preflight same-net multi-pad warning remains. No manufacturing files were exported.
Exact completed edits
BOM and authoritative parts
  • C2, C6, C10: GRM32ER71E226KE15L, LCSC C21397, 22 uF 25 V, changed to SMD_1210_3225Metric.
  • J8: MPN 0026603060, LCSC C3334024, 6-position right-angle THT, 3.96 mm pitch.
  • J9: MPN 0026602080, LCSC C3335525, 8-position single-row THT, 3.96 mm pitch.
  • U8 property readback corrected to MB85RS256TYPNF-GS-BCERE1, LCSC C190125, SOP-8; the correct library part was already instantiated.
  • U17 property readback corrected to 74LVC125AD,112, LCSC C548083, SOP-14; the correct library part was already instantiated.
  • U19-U26 confirmed as PC817C, LCSC C115500, DIP-4. Obsolete SMD pad/envelope overrides were removed, restoring the through-hole DIP footprint.
  • X1 confirmed as X322516MLB4SI, LCSC C13738, SMD3225-4P. Pins 2 and 4 remain on GND; pins 1 and 3 remain the two active crystal nets.
TP1 override
  • TP1 remains a bare 1.0 x 1.0 mm top-side SMD pad.
  • Marked DNP by Exclude from BOM=true and Exclude from Pick & Place=true.
  • Disconnected from TEST_CLAMP_NODE and connected directly to the same net as J1 pin 3.
  • Verified resulting net name: GND.
  • TP1 has the global +0.05 mm solder-mask opening and component silkscreen is suppressed, so its pad is not crossed by footprint silk.
Board and fabrication configuration
  • Board: 100.0 x 100.0 mm, rectangular, four copper layers.
  • Stackup configured as JLCPCB JLC041621-7628, ENIG, Dk 4.4, 2 oz Top/Bottom and 1 oz inner copper.
  • Layer assignment: Top signal, Mid-Layer 1 ground plane, Mid-Layer 2 power plane, Bottom signal.
  • General trace width: 0.20 mm.
  • General copper clearance: 0.20 mm.
  • Copper-to-edge inset: 0.30 mm.
  • Via minimum: 0.35 mm diameter / 0.15 mm finished drill.
  • Pad solder-mask expansion: +0.05 mm, including hole-edge expansion.
  • Component-local silkscreen lines/text/circles/rectangles were suppressed to eliminate the pervasive thin-line and silk-to-pad/hole DFM class. Board-level silk can be added later if desired.
Placement result
  • Top components: 170.
  • Bottom components: 0.
  • Component body overlaps: 0.
  • Out-of-bounds components: 0.
  • Keepout violations returned by placement checks: 0.
  • Aggregate component bounds: 98.71 x 98.87 mm inside the 100 x 100 mm board.
Connector drill/pitch confirmation
  • J8 pad centers: +9.90, +5.94, +1.98, -1.98, -5.94, -9.90 mm: 3.96 mm consecutive pitch, six holes.
  • J9 pad centers: +13.86, +9.90, +5.94, +1.98, -1.98, -5.94, -9.90, -13.86 mm: 3.96 mm consecutive pitch, eight holes.
  • J8/J9 drill diameter: 1.7526 mm; copper pad diameter: 2.2606 mm, giving about 0.254 mm radial annular ring.
Current validation evidence
Routing state
  • Airwires: 361.
  • Existing vias: 24.
  • Fully routed nets: not established; the board remains predominantly unrouted.
Routing preflight
After removing the conflicting ADuM pad rules, all different-net overlapping-pin warnings cleared. One warning remains:
  • Q6 has five overlapping drain pads on the same BOOST_SW net. The router treats them as one pin. This is normally intentional for a multi-pad power MOSFET, but the footprint should be reviewed before final release.
Two advisory via-at-SMD notices remain for exposed pads.
DRC/ERC blockers
  • No open findings in the queried checks for missing footprints, invalid layers, component body overlap, component outside board, different-net copper overlap, dangling traces, trace overlap, or stackup validation.
  • ERC blocker: TEST_CLAMP_NODE now contains only D2:A. This was intentionally not reconnected or repurposed because the user prohibited inferred circuitry. It requires schematic-owner disposition: correct net assignment or an explicit no-connect decision.
  • Routing blocker: 361 airwires.
  • External JLCDFM categories have not been re-scanned against fresh Gerbers; therefore zero findings cannot be claimed for soldermask bridges/openings, plated slots, or final silk geometry.
Differential pairs and current paths
  • No paid ±10% impedance-control service is intended.
  • The configured stackup supports routing USB 2.0 and 10/100 Ethernet pairs over a continuous Mid-Layer 1 GND reference, but the pairs have not yet been routed. No guaranteed impedance is claimed.
  • Final pair routing must be coupled, symmetric, minimally via'd, and intra-pair matched.
  • Final power/current review is still required after routing for protected 12 V, 5 V, 3.3 V, boost/PSE, pass-FET, shunt and connector paths. Outer copper is 2 oz, but 1 oz inner transitions and via arrays can remain limiting. No conservative widths should be reduced.
Smallest remaining worklist
  1. Resolve or formally accept/review the Q6 same-net multi-drain-pad routing warning.
  2. Route all 361 airwires, starting with power/high-current paths, then USB/Ethernet differential pairs, then remaining signals.
  3. Add adequate parallel vias and neckdowns for power transitions; verify voltage drop/current density with 2 oz outer and 1 oz inner copper.
  4. Resolve the single-pin TEST_CLAMP_NODE at D2:A without inferring a new function.
  5. Run full DRC and signal/power-integrity checks; confirm zero airwires and no blocking copper errors.
  6. Generate fresh Gerbers and run JLCDFM to verify all nine reported categories, including plated slots and final mask geometry.
  7. Perform the final row-by-row 85-row BOM readback audit and only then export Gerber, BOM and pick-and-place files.
Export gate
FAIL — manufacturing export is not permitted yet. Blocking reasons: 361 airwires, unresolved D2:A single-pin net, Q6 footprint preflight warning, incomplete final power/differential routing review, and no fresh JLCDFM verification.

  • Overall result

  • Scope status

  • Exact completed edits

  • BOM and authoritative parts

  • TP1 override

  • Board and fabrication configuration

  • Placement result

  • Connector drill/pitch confirmation

  • Current validation evidence

  • Routing state

  • Routing preflight

  • DRC/ERC blockers

  • Differential pairs and current paths

  • Smallest remaining worklist

  • Export gate