• U5 ESP32-S3-WROOM-1U-N16R8: ESP-IDF 5.x, target esp32s3.
• U4 ATMEGA1284P-AU: avr-gcc/avr-libc, 16 MHz external crystal.
• Product-specific command framing, authentication, telemetry schemas, serial selection policy, and PSE operating policy are explicitly marked application TODOs.

C
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "driver/i2c_master.h"
#include "driver/spi_master.h"
#include "driver/spi_slave.h"
#include "esp_check.h"
#include "esp_log.h"

#define ETH_SCLK 10
#define ETH_MOSI 11
#define ETH_MISO 12
#define ETH_CS_LAN 13
#define ETH_CS_DISPLAY 14
#define ETH_INT_LAN 15
#define ETH_INT_DISPLAY 16
#define ETH_RST_LAN 17
#define ETH_RST_DISPLAY 18
#define AVR_SPI_SCLK 5
#define AVR_SPI_MOSI 6
#define AVR_SPI_MISO 7
#define AVR_SPI_CS 8
#define AVR_RESET 9
#define PSE_SCL 35
#define PSE_SDA 36
#define PSE_INT 37
#define PSE_RESET 38
#define PSE_SHUTDOWN 39

static const char *TAG = "intercede";
static i2c_master_bus_handle_t pse_i2c;
static spi_device_handle_t w5500_lan, w5500_display;

static void gpio_safe_defaults(void) {
    gpio_config_t out = {.pin_bit_mask = (1ULL<<ETH_CS_LAN)|(1ULL<<ETH_CS_DISPLAY)|
        (1ULL<<ETH_RST_LAN)|(1ULL<<ETH_RST_DISPLAY)|(1ULL<<AVR_RESET)|
        (1ULL<<PSE_RESET)|(1ULL<<PSE_SHUTDOWN), .mode = GPIO_MODE_OUTPUT};
    ESP_ERROR_CHECK(gpio_config(&out));
    gpio_set_level(ETH_CS_LAN, 1); gpio_set_level(ETH_CS_DISPLAY, 1);
    gpio_set_level(ETH_RST_LAN, 0); gpio_set_level(ETH_RST_DISPLAY, 0);
    gpio_set_level(AVR_RESET, 0);
    gpio_set_level(PSE_SHUTDOWN, 0); gpio_set_level(PSE_RESET, 0);
    gpio_config_t in = {.pin_bit_mask=(1ULL<<ETH_INT_LAN)|(1ULL<<ETH_INT_DISPLAY)|(1ULL<<PSE_INT),
        .mode=GPIO_MODE_INPUT, .pull_up_en=GPIO_PULLUP_ENABLE};
    ESP_ERROR_CHECK(gpio_config(&in));
}

static void init_pse_i2c(void) {
    i2c_master_bus_config_t cfg = {.i2c_port=I2C_NUM_0, .sda_io_num=PSE_SDA,
        .scl_io_num=PSE_SCL, .clk_source=I2C_CLK_SRC_DEFAULT, .glitch_ignore_cnt=7,
        .flags.enable_internal_pullup=true};
    ESP_ERROR_CHECK(i2c_new_master_bus(&cfg, &pse_i2c));
}

static void init_w5500_spi(void) {
    spi_bus_config_t bus = {.sclk_io_num=ETH_SCLK,.mosi_io_num=ETH_MOSI,.miso_io_num=ETH_MISO,
        .quadwp_io_num=-1,.quadhd_io_num=-1,.max_transfer_sz=2048};
    ESP_ERROR_CHECK(spi_bus_initialize(SPI2_HOST, &bus, SPI_DMA_CH_AUTO));
    spi_device_interface_config_t dev = {.clock_speed_hz=20000000,.mode=0,.spics_io_num=-1,.queue_size=4};
    ESP_ERROR_CHECK(spi_bus_add_device(SPI2_HOST, &dev, &w5500_lan));
    ESP_ERROR_CHECK(spi_bus_add_device(SPI2_HOST, &dev, &w5500_display));
    /* TODO(application): implement W5500 variable-length data mode and manually assert the selected CS only. */
}

static void init_avr_spi_slave(void) {
    spi_bus_config_t bus = {.sclk_io_num=AVR_SPI_SCLK,.mosi_io_num=AVR_SPI_MOSI,
        .miso_io_num=AVR_SPI_MISO,.quadwp_io_num=-1,.quadhd_io_num=-1,.max_transfer_sz=256};
    spi_slave_interface_config_t slv = {.spics_io_num=AVR_SPI_CS,.mode=0,.queue_size=3};
    ESP_ERROR_CHECK(spi_slave_initialize(SPI3_HOST, &bus, &slv, SPI_DMA_CH_AUTO));
    /* TODO(application): queue framed full-duplex transactions; define CRC, command IDs and READY semantics in protocol. */
}

void app_main(void) {
    gpio_safe_defaults();
    init_pse_i2c();
    init_w5500_spi();
    init_avr_spi_slave();
    vTaskDelay(pdMS_TO_TICKS(20));
    gpio_set_level(AVR_RESET, 1);
    gpio_set_level(ETH_RST_LAN, 1); gpio_set_level(ETH_RST_DISPLAY, 1);
    /* Keep PSE_RESET low until PSE_54V is bench-verified. Then release RESET, wait >=22 ms,
       read the TPS23861 identity/status, and only then deassert SHUTDOWN per product policy. */
    ESP_LOGI(TAG, "safe interfaces initialized; PSE remains disabled");
    while (1) vTaskDelay(pdMS_TO_TICKS(1000));
}

Sh
idf.py set-target esp32s3
idf.py build

C
#define F_CPU 16000000UL
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/twi.h>
#include <util/delay.h>

#define FRAM_CS PB3
#define ESP_CS  PB4

static void gpio_init(void) {
    DDRA = 0xF0;                 /* PA0-3 inputs; PA4-7 outputs */
    PORTA = 0x00;                /* outputs default inactive; external pull-ups serve inputs */
    DDRD = _BV(PD1)|_BV(PD2)|_BV(PD3)|_BV(PD4);
    PORTD = _BV(PD2)|_BV(PD3)|_BV(PD4); /* all serial receivers deselected */
}

static void spi_init(void) {
    DDRB |= _BV(FRAM_CS)|_BV(ESP_CS)|_BV(PB5)|_BV(PB7);
    DDRB &= ~_BV(PB6);
    PORTB |= _BV(FRAM_CS)|_BV(ESP_CS);
    SPCR = _BV(SPE)|_BV(MSTR)|_BV(SPR0); /* mode 0, F_CPU/16 */
}
static uint8_t spi_xfer(uint8_t v){ SPDR=v; while(!(SPSR&_BV(SPIF))); return SPDR; }

static void twi_init(void) {
    TWSR = 0; TWBR = 72; /* 100 kHz at 16 MHz */
    TWCR = _BV(TWEN);
}

static void uart0_init_9bit(uint16_t ubrr) {
    UBRR0H = (uint8_t)(ubrr>>8); UBRR0L=(uint8_t)ubrr;
    UCSR0B = _BV(RXEN0)|_BV(TXEN0)|_BV(RXCIE0)|_BV(UCSZ02);
    UCSR0C = _BV(UCSZ01)|_BV(UCSZ00); /* 9 data bits, 1 stop, no parity */
}
static void uart0_put9(uint16_t v) {
    while(!(UCSR0A&_BV(UDRE0)));
    if(v&0x100) UCSR0B|=_BV(TXB80); else UCSR0B&=~_BV(TXB80);
    UDR0=(uint8_t)v;
}

static volatile uint8_t machine_edges;
ISR(PCINT0_vect) { machine_edges |= (PINA & 0x0F); }
ISR(USART0_RX_vect) {
    uint16_t word = (UCSR0B & _BV(RXB80)) ? 0x100 : 0;
    word |= UDR0;
    (void)word; /* TODO(application): selected SAS/COM framing and message parser. */
}

static void machine_irq_init(void) {
    PCICR |= _BV(PCIE0); PCMSK0 = 0x0F; /* PA0..PA3 */
}

int main(void) {
    cli(); gpio_init(); spi_init(); twi_init(); uart0_init_9bit(16); /* 57600 baud */
    machine_irq_init(); sei();
    for (;;) {
        PORTB &= ~_BV(ESP_CS);
        uint8_t status = spi_xfer(0x00); /* TODO(application): replace with framed command/CRC protocol. */
        PORTB |= _BV(ESP_CS);
        (void)status;
        _delay_ms(10);
    }
}

Sh
avr-gcc -mmcu=atmega1284p -DF_CPU=16000000UL -Os -o main.elf src/main.c
avr-objcopy -O ihex -R .eeprom main.elf main.hex

1. U5 boots with both W5500 resets asserted, U4 reset asserted, and TPS23861 RESET/SHUTDOWN asserted.
2. U5 initializes GPIO and buses, then releases U4 and W5500 resets.
3. U4 immediately owns machine inputs/outputs, serial selection, 9-bit UART, FRAM, RTC, and secure element.
4. U5 verifies the 54 V rail before releasing TPS23861 reset. Wait at least 22 ms after reset release before I2C access.
5. TODO(application): define ESP↔AVR framed messages, watchdog/heartbeat behavior, replay protection, Ethernet addressing, secure-element provisioning, RTC policy, and exact TPS23861 register configuration.