Ethernet and PoE Architecture Resolution
Status: Pending operator confirmation
Date: 2026-08-20
Authoritative interpretation from latest clarification
Controller board
MAIN NETWORK RJ45 -> discrete Ethernet magnetics -> W5500 #1 -> controller MCU/processing domain.- Controller processing domain ->
W5500 #2 -> discrete Ethernet magnetics -> DISPLAY RJ45.
- The controller is powered from 12 V ATX/barrel input, not from upstream PoE.
- The 12 V source is boosted to approximately 48-52 V.
- A
TPS23861PW PSE stage injects negotiated PoE onto the display Ethernet cable.
- The controller therefore has one ordinary upstream Ethernet data port and one downstream Ethernet + PoE PSE port.
- The two W5500 devices require independent
CS, INT, and RST signals; clock/data may share an SPI bus if the selected controller architecture and firmware support it.
Display board
DISPLAY RJ45 receives Ethernet data and negotiated PoE power.- Ethernet data passes through discrete magnetics to
LAN8742AI-CZ-TR, then by RMII to STM32H743ZGT6.
- PoE power is accepted by
TPS23751PWP and converted to the display-side 5 V rail.
- The 5 V rail powers the display, RFID, RTC, ATECC, ESP32-C6, and LEDs, subject to the final display-board power budget and authentication-gating requirements.
Clauses superseded in the earlier PoE specification
The following earlier requirements conflict with the latest architecture and must not be implemented on the controller schematic:
- Controller as an IEEE 802.3bt Type 3/Class 6 upstream PD.
- Upstream Mode A/Mode B PoE bridge, detection signature, classification, hot-swap, MPS, and isolated 36-57 V to 12 V converter on the controller.
- OR-ing of PoE-derived 12 V with the controller barrel/ATX 12 V source.
- Display-side W5500 and ESP32-S3 as the primary wired Ethernet endpoint.
- Statement that both controller ports are PoE hops.
Requirements retained
- Two Ethernet interfaces on the controller.
- Real negotiated PoE on the controller-to-display cable; no passive injection.
- Downstream display power delivered with a standards-compliant PSE/PD handshake.
- Discrete non-mag RJ45 connectors and discrete Ethernet magnetics where required by the selected injection/extraction topology.
- Independent Ethernet reset, interrupt, and chip-select control.
- Hardware hooks to keep RFID, LEDs, and credit/application functions disabled until authentication succeeds.
- Fail-safe disable after link or authentication loss.
- Separation of logic ground, isolated machine ground, and chassis/shield domain.
Blocking confirmation required
Before schematic capture, confirm these points:
- The controller has no incoming PoE PD circuitry; its only power input is the protected 12 V ATX/barrel domain.
- The controller contains two W5500 devices: one for the main-network RJ45 and one for the display RJ45.
- The display board uses LAN8742AI-CZ-TR + STM32H743ZGT6, not a display-side W5500 as stated in the older PoE spec.
TPS23861PW is the locked controller PSE controller and TPS23751PWP is the locked display PD/flyback controller.- The latest clarification diagram supersedes conflicting portions of the build prompt, PoE specification, lessons-learned file, and stale BOM rows.
Design gate after confirmation
A new controller power budget is required before selecting the 12 V-to-48/52 V boost stage, PSE current limit, fuse, MOSFETs, magnetics current rating, bulk capacitance, and input connector/current rating. The display's maximum 5 V load and PoE class must be fixed at that gate.