The controller design assumes a clean, regulated 12 VDC input. The LM5155 UVLO remains final at approximately 11.0 V ON / 10.5 V OFF. A source producing materially other than 12 VDC is an external supply fault to correct by replacing/repairing the supply, not a condition requiring controller redesign.
The 10.8 V cold-start item is resolved and is not a blocker. Use 10.8 V only as an analytical hold-up/survival corner after normal startup.
Equipment and safety
Use a current-limited bench source, DMM, oscilloscope, isolated/appropriate differential probes for the 54 V and switch node, thermal camera, USB isolator where needed, and a known-good non-PoE Ethernet peer. Keep the downstream PoE cable disconnected until the explicit PSE stage.
Stage 0 — unpowered inspection
Confirm no shorts between +12V_IN, VIN_PROT, +5V, +3V3, PSE_54V, GND, ISO_GND, and MACH_COM.
Confirm BT1 polarity: holder + to RTC_VBAT/U9 VBAT; holder negative to GND. Install a non-rechargeable CR2032 only after polarity checks.
Confirm Q6/D4/L3 orientation and Q5 low-side PSE orientation.
Confirm T1B PHY-side center taps pins 2 and 7 are on +3V3, not GND.
Pass: no rail-to-ground resistance below 10 Ω after capacitor charging effects settle; no cross-domain short. Fail: stop and locate the short.
Stage 1 — regulated 12 V input and local rails only
Remove CR2032. Disconnect Ethernet, machine I/O, and isolated serial loads.
Apply 12.0 V with a 0.25 A current limit. Do not permit the PSE to start; R76 must hold PSE_RESET_N low until U5 drives it high.
Verify VIN_PROT, +5V, and +3V3.
Table
Node
Pass band
+12V_IN
11.8–12.2 V
VIN_PROT
within 0.5 V of +12V_IN at light load
+5V
4.85–5.15 V
+3V3
3.20–3.40 V
PSE_RESET_N before firmware release
<0.4 V
Fail on current-limit operation, smoke/odor, rail oscillation, or any local regulator exceeding 70 °C at no load.
Stage 2 — MCU programming and safe-state firmware
Program U5 through native USB or J7 UART0 using J7 IO0/EN controls.
Program U4 through J7 pins 1–6 using AVR ISP.
Load the safe starter firmware: machine outputs inactive, serial receivers deselected, W5500 reset initially low, TPS23861 RESET and SHUTDOWN low.
Verify U5 can reset U4 through AVR_RESET.
Pass: both devices program and reset repeatedly; U4 clock measures 16 MHz; no boot loop; U5 strap pins produce normal SPI-flash boot unless IO0 is intentionally grounded during reset.
Stage 3 — MCU communication, FRAM, RTC, secure element
Exercise the U4-master SPI link to U5 with FRAM_CS_N and AVR_SPI_SS mutually exclusive.
Read/write/verify multiple FRAM addresses.
Scan AVR I2C: DS3231 at 0x68 and provisioned ATECC608B address expected by firmware.
Set/read RTC time on +5 V, then remove 12 V with CR2032 installed and verify retention.
Pass: zero SPI contention, 1000 loopback frames without CRC/application framing error, FRAM pattern passes, RTC drift/retention continues across a 10 minute outage, VBAT is 2.7–3.3 V, and no measurable positive charge current is driven into the CR2032 (DMM resolution target <1 µA external path).
Stage 4 — Ethernet data paths, PoE still disabled
Keep PSE_RESET_N low and downstream cable unpowered.
Release U7/U7B resets; verify each W5500 independently using shared SCK/MOSI/MISO and separate CS/INT/RESET.
Connect LAN port and downstream data port to known-good Ethernet peers without applying PoE.
Pass: each W5500 has a unique accessible register set, only the selected MISO driver is active, 100BASE-T link is stable for 10 minutes, and packet loss is <0.1% over 10,000 local packets. Fail on shared-bus contention or magnetics/common-mode heating.
Stage 5 — 54 V boost with TPS23861 held reset
Raise bench input current limit gradually to 6 A capability while maintaining 12.0 V.
Keep TPS23861 RESET low and downstream RJ45 disconnected.
Observe PSE_54V startup, switch node, Q6/D4 temperature, and input current.
Pass criteria:
PSE_54V = 52.5–55.5 V at light load.
No sustained switch-node excursion above 120 V; investigate any ringing approaching the 150 V Q6 rating.
No-load input current is stable and no power component exceeds 70 °C after 10 minutes.
At 20 W and 40 W resistive/electronic load, rail remains 51.8–55.5 V and no component exceeds its thermal limit; use a provisional 100 °C case stop limit for Q6/D4/C76 pending final thermal characterization.
UVLO bench sweep confirms typical turn-on near 11.0 V and turn-off near 10.5 V. Do not require cold-start at 10.8 V.
Stage 6 — TPS23861 and one-port PSE
Confirm PSE_54V is in range before U5 drives PSE_RESET_N high.
Keep PSE_SHUTDOWN_N low initially. After reset release wait at least 22 ms before I2C access.
Read identity/status, configure only port 1, confirm ports 2–4 remain disabled, then release shutdown according to the chosen register policy.
Test first with an IEEE 802.3at analyzer/load, then the intended display PD.
Pass: valid detect/classification, no power on open/short/non-PD loads, port voltage 44–57 V, current limit/foldback operates without Q5 SOA distress, and Type-2 delivered power supports the required 25.5 W PD budget. Verify F2 and D3 remain cool during normal operation and coordinate safely during a controlled fault.
Stage 7 — isolated machine interfaces
Verify ISO_5V_SAS and ISO_5V_COM independently; confirm no DC continuity from ISO_GND/MACH_COM to logic GND.
Apply 5 V then 12 V test signals to each PC817 field input through the intended connector.
Exercise credit-return, credit-inject, error-lamp, and system-enable outputs into representative loads.
Exercise SAS/COM1/COM2 receive selection one at a time and verify 9-bit USART behavior.
Pass: input thresholds switch cleanly, R60–R63 remain below 60 °C at continuous 12 V, no two receive paths are enabled simultaneously, isolation domains remain separated, and output inactive states are maintained during both MCU resets.
Stage 8 — surge, thermal, and dynamic validation before layout release
These are bench/layout gates, not schematic rewiring tasks:
LM5155 Bode injection and 20↔40 W load-step capture.
Q6/D4 hot-loop and overshoot measurement with a low-inductance probe.
TPS23861 Kelvin accuracy and Q5 SOA during classification/inrush/fault.
PSE fuse/TVS surge coordination.
Creepage/clearance review between 54 V, Ethernet magnetics, chassis, logic, ISO_GND, and MACH_COM.
Thermal soak at maximum ambient/load.
Pass only after measurements are archived and all components remain within derated voltage, current, ripple, and temperature limits.
Canonical input assumption
Equipment and safety
Stage 0 — unpowered inspection
Stage 1 — regulated 12 V input and local rails only
Stage 2 — MCU programming and safe-state firmware
Stage 3 — MCU communication, FRAM, RTC, secure element
Stage 4 — Ethernet data paths, PoE still disabled
Stage 5 — 54 V boost with TPS23861 held reset
Stage 6 — TPS23861 and one-port PSE
Stage 7 — isolated machine interfaces
Stage 8 — surge, thermal, and dynamic validation before layout release