Carrier Board Schematic
ok so I moved things a little bit more together / inward. Are thing still fine in the left side of the board, below the Xiao? It's a little busy down there.
Additionally I moved things in a little so can you try and shave down on the extra pcb around the edges that doesnt need to be there?
I have included a screenshot and then an edited version of the screenshot, where I have made a new layout box in red.
The usb C ports were oddly 'in land' before and this would put them on the edge of the board where they belong.
Image
Image
Thought for 9 sec
I’ll inspect the current left-side/XIAO clearance and component bounds, then shrink the outline around the actual placement so J7/J8 sit correctly at the edge. I’ll avoid moving components unless the tighter outline exposes a real clearance problem, then run board-edge and overlap checks.
Worked for 6 mins 10 sec
The busy area below the XIAO is still valid: no component-body, copper, pad-access, or module-shadow conflicts were found.
I trimmed the board to a custom outline following your red box, with J7/J8 now aligned to the right board edge. All parts remain top-side and pass board-edge/overlap checks. The effective board area dropped from 8000 mm² to 7687 mm²; Flux normalized the coordinate origin, but relative placement was preserved aside from D1/D2 shifting approximately 0.5 mm inward.
Check edge and labels
Verify left side
Route power first
Fix D1 D2 shift
Review USB alignment
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Project Specification
Project Overview
- Status: Draft — schematic phase
- Compact Raspberry Pi Compute Module 5 carrier hosting a removable Seeed XIAO ESP32-S3-class module.
- Target board: approximately 70 × 60 mm, 4 layers. Full-board placement and routing remain out of scope for this revision.
Intended Use
Prototype/validation carrier providing CM5 compute, an auxiliary socketed XIAO controller, robust USB-C power, storage/boot support, and service/debug access. RTC functionality is provided by an external I2C module on Qwiic/STEMMA-QT.
Main Features
- CM5 on two Amphenol 10164227-1001A1RLF 100-position board-to-board receptacles, 1.5 mm stack.
- USB-C power input matching official CM5IO architecture and a separate rpiboot/device USB-C interface.
- XIAO socket: two top-face 1×7 through-hole female socket headers, 2.54 mm pitch and exactly 15.24 mm row-center spacing.
- The XIAO is fitted with downward male pins and plugs removably into the carrier, matching the Seeed Round Display assembly; no soldered castellated-pad mounting.
- microSD, 4-pin PWM fan, Qwiic/STEMMA-QT, UART console, buttons, and LEDs.
- No onboard RTC battery, battery holder, charger, or VBAT network.
XIAO Socket Orientation and Pin Positions
Datum is the official XIAO top view with the USB-C connector at the top/outboard end. The carrier sockets are on the carrier top face. Both rows run inward from the USB end at 2.54 mm pitch.
- Left row J3 is mirrored: top/outboard to bottom/inboard = pin 7 D0/A0, pin 6 D1/A1, pin 5 D2/A2, pin 4 D3/A3, pin 3 D4/SDA, pin 2 D5/SCL, pin 1 D6/TX.
- Right row J4: top/outboard to bottom/inboard = pin 1 5V, pin 2 GND, pin 3 3V3, pin 4 D10/MOSI, pin 5 D9/MISO, pin 6 D8/SCK, pin 7 D7/RX.
- Used carrier connections: J3 pin 1 D6/TX → CM5 GPIO5 UART2 RX through 33 Ω; CM5 GPIO4 UART2 TX through 33 Ω → J4 pin 7 D7/RX; J4 pin 1 receives isolated/switched 5 V; J4 pin 2 is GND; J4 pin 3 is CM5 3.3 V.
- Remaining header positions are intentionally unconnected on this carrier.
- At final layout, the USB-C end must be at a carrier edge with the connector accessible at or beyond the outline. The pin-1/outboard landmark and USB direction must be shown on silkscreen.
External RTC Plan
- The CR2032 holder and CM5 VBAT connection are removed.
- CM5 VBAT pin 76 is intentionally left unconnected; no invented recharge, diode, or battery circuitry is fitted.
- External RTC connects through Qwiic/STEMMA-QT using CM5 GPIO2 = SDA and GPIO3 = SCL, with 3.3 V and GND.
- Existing carrier I2C pull-ups remain; attached RTC-board pull-ups must be included when checking total bus pull-up resistance.
System Architecture
Text
5.1V/5A USB-C PD |-- CC1/CC2 + ESD --> CM5 built-in PD sink `-- VBUS protection/bulk --> CM5 5V `--> GPIO23 load switch --> reverse blocking --> XIAO 5V CM5 GPIO4/5 UART2 --> XIAO D7/D6 socket positions CM5 GPIO2/3 I2C --> Qwiic/STEMMA-QT --> external RTC module CM5 VBAT: intentionally unconnected
Power and Runtime Expectations
- External regulated 5.1 V USB-C PD source, 5 A capability.
- No battery power, onboard RTC battery, or battery charger.
- XIAO may simultaneously have its own USB-C connected; carrier power path must block reverse current in both source conditions.
Manufacturing and Assembly Expectations
- 4-layer PCB, professional SMD assembly except the two through-hole 1×7 female XIAO sockets.
- XIAO plugs from above using downward male header pins.
- Verified MPNs/footprints for non-generic parts; Amphenol 10164227-1001A1RLF is must-not-substitute.
Physical Design Expectations
- Approx. 70 × 60 mm, four M2.5 holes.
- XIAO row center spacing is 15.24 mm; each row is 7 positions at 2.54 mm pitch.
- Final board outline/edge datum is not locked in this revision. Preserve the encoded socket pair and place its common USB end at the selected edge during layout.
Authoritative Sources
- Raspberry Pi Compute Module 5 datasheet RP-008180-DS.
- Official Seeed Studio XIAO Series Package and PCB Design drawing.
- Seeed Studio Round Display for XIAO v1.1 schematic and assembly guidance.
Project Overview
Intended Use
Main Features
XIAO Socket Orientation and Pin Positions
External RTC Plan
System Architecture
Power and Runtime Expectations
Manufacturing and Assembly Expectations
Physical Design Expectations
Authoritative Sources
