Project Idea Start

Thought for 4 mins 11 sec
Thought for 6 sec
Checking Build schematic and place PCB progress…
Thought for 9 sec — Considering progress updates
Steering Build schematic and place PCB…
Thought for 8 sec
Awaiting 1 background task
Thought for 7 sec
Checking ESP32 Triple Screen Dashboard progress…
Received notification from "ESP32 Triple Screen Dashboard" that it finished — picking the work back up.

flux

Schematic and placement are complete, and the routing precheck is clean. I’m starting the full-board route now, then I’ll check for any remaining airwires or DRC issues.

flux

Built and routed the ESP32 Triple Screen Dashboard motherboard:
  • Complete 9-component schematic with three ILI9341 sockets
  • 165 × 55 mm, 2-layer PCB
  • All components placed on the top layer
  • ESP32 USB faces the left board edge
  • Autorouter converged with 0 airwires
  • No placement or routing feasibility issues
Open item
  • One false-positive ERC remains: the library ESP32 DevKit part incorrectly classifies unused VP/GPIO36 as a power input. It was marked intentionally unconnected; connecting it to power would be electrically wrong.
  • GPIO2, GPIO5, and GPIO15 are ESP32 boot-strapping pins. The requested wiring is preserved, but attached displays must not force incorrect levels during startup.
Add boot-safe circuits
Create firmware starter
Prepare bring-up plan
Review manufacturing readiness
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Files

Schematic

Layout

Preview

Project Specification
Project Overview
  • Status: Approved for implementation from the supplied requirements.
  • ESP32 development-board motherboard for three ILI9341-compatible SPI display modules.
Intended Use
  • Hobbyist dashboard prototype using plug-in 1×9 display modules and an ESP32 DevKit board.
What the Device Should Do
  • Power three displays from the ESP32 DevKit 3.3 V rail.
  • Share SPI clock, MOSI, MISO, reset, and D/C.
  • Provide one independent chip-select per display.
Main Features
  • One ESP32-WROOM-32-family DevKit module with onboard USB and regulator.
  • Three 2.54 mm-pitch, 1×9 female through-hole display sockets.
  • Local 100 nF decoupling per display, 100 uF rail bulk capacitance, and a 10 kΩ Screen2 CS pull-up.
System Architecture
Text
USB → ESP32 DevKit 3V3/GND → Screen1 / Screen2 / Screen3
ESP32 shared SPI + control → all three screens
ESP32 GPIO5 / GPIO15 / GPIO21 → individual screen CS pins
Hardware Subsystems
  • Controller: ESP32 DevKit board-level module.
  • Display interfaces: Three identically pinned 1×9 sockets.
  • Power support: One 100 uF electrolytic plus three 100 nF ceramics.
  • Configuration: 10 kΩ pull-up on Screen2 CS.
Interfaces and Connections

Table

Screen pinSignal
1VCC / 3V3
2GND
3CS (individual)
4TFT_RESET / GPIO4
5TFT_DC / GPIO2
6SPI_MOSI / GPIO23
7SPI_SCK / GPIO18
8LED / 3V3
9SPI_MISO / GPIO19
Chip selects: Screen1 GPIO5, Screen2 GPIO15, Screen3 GPIO21.
Power and Runtime Expectations
  • Power is supplied through the selected ESP32 development board USB input and onboard 3.3 V regulator.
  • Display-module current and backlight current must remain within the development board regulator capability; exact display-module load is not specified.
Power Tree and Power Budget
  • USB input → ESP32 DevKit onboard regulator → 3V3 net → all display VCC and LED pins.
  • No separate regulator or protection circuitry is in scope.
Manufacturing and Assembly Expectations
  • Standard 2-layer PCB.
  • 165 mm × 55 mm rectangular outline.
  • All components top-side.
  • SMD small passives; through-hole display sockets and ESP32 DevKit carrier footprint.
Firmware-Relevant Hardware Requirements
  • Shared SPI: SCK GPIO18, MOSI GPIO23, MISO GPIO19.
  • Shared controls: RESET GPIO4, D/C GPIO2.
  • CS: GPIO5, GPIO15, GPIO21.
Physical Design Expectations
  • ESP32 at far left with USB accessible from the left edge.
  • Screen sockets arranged horizontally from middle-left to middle-right.
  • Antenna area kept at an edge with no nearby components/copper where the footprint exposes a keepout.
  • No routing in this design stage.
Important Design Decisions
  • Use a Flux-library ESP32 DevKitC board-level footprint as the available standard ESP32-WROOM-32 DevKit-style implementation.
  • Preserve GPIO2, GPIO5, and GPIO15 assignments exactly as requested.
Assumptions
  • Plug-in display modules accept 3.3 V power and 3.3 V logic at the specified 1×9 pin order.
  • The display headers are vertical female socket strips.
Change Notes
  • Initial schematic and PCB setup specification captured.
Boot-strapping warning: GPIO2, GPIO5, and GPIO15 are ESP32 strapping-related pins. External display circuitry or pull states can affect boot. The requested mapping is intentionally preserved; disconnect displays during recovery if boot/programming problems occur.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes