Added initial discrete logic parts to start the adder/subtractor build: Q121–Q130 (2N2222A) and R401–R420 (Generic Resistors, default 10k, axial).
Test headers already present in the project: J1, J2, J3, J4, J5, J6.
Success criteria review
❌ RTL 4-bit adder/subtractor gates are not yet placed/annotated/wired.
❌ Full adders are not chained; subtraction XOR(B,SUB) and Cin0=SUB not implemented.
❌ Flags (C/Z/V/N) not generated nor wired to headers.
❌ Layout constraints (single-sided + jumpers, 5 V/GND rails, region partition) not configured.
Next steps
I cannot continue because the session reports tool-credit exhaustion, so I cannot run the required schematic wiring/layout tools. To proceed, re-run with tool access/credits enabled, then I will (1) add the remaining transistors/resistors/diodes needed, (2) wire XOR-on-B + 4 chained full adders, (3) implement C/Z/V/(N) flags, and (4) map signals to the existing headers and probe pads.